82801DB Datasheet, PDF (447/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

EHCI Controller Registers (D29:F7)
12.2.3 USB 2.0-Based Debug Port Register
The Debug port’s registers are located in the same memory area, defined by the Base Address
Register (BAR), as the standard EHCI registers. The base offset for the debug port registers (80h)
is declared in the Debug Port Base Offset Capability Register at Configuration offset 5Ah. The
specific EHCI port that supports this debug capability is indicated by a 4-bit field (bits 20–23) in
the HCSPARAMS register of the EHCI controller.
The map of the Debug Port registers is shown in Table 12-4. Each register is defined individually
below.
Table 12-4. Debug Port Register Address Map
Offset
Register Name
00h Control/Status
04h USB PIDs
08h Data Buffer (Bytes 3:0)
0Ch Data Buffer (Bytes 7:4)
10h Config Register
Type
R/W, RO
R/W, RO
R/W
R/W
R/W
NOTES:
1. All of these registers are implemented in the core well and reset by PCIRST#, EHC HCRESET, and a EHC
D3-to-D0 transition.
2. The hardware associated with this register provides no checks to ensure that software programs the interface
correctly. How the hardware behaves when programmed illegally is undefined.
12.2.3.1
Control/Status Register
Offset:
Default Value:
00h
00000000h
Attribute: R/W, RO
Size:
32 bits
Note: Software should do Read-Modify-Write operations to this register to preserve the contents of bits
not being modified. This include Reserved bits.
Note: To preserve the usage of RESERVED bits in the future, software should always write the same
value read from the bit until it is defined. Reserved bits will always return 0 when read.
Bit
Description
31 Reserved
OWNER_CNT — R/W.
0 = Default.
30 ^{1 = Ownership of the debug port is forced to the EHCI controller (i.e., immediately taken away}
from the companion Classic USB Host controller). If the port was already owned by the EHCI
controller, then setting this bit has no effect. This bit overrides all of the ownership-related bits
in the standard EHCI registers.
29 Reserved
Intel^® 82801DB ICH4 Datasheet
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