82801DB Datasheet, PDF (509/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

AC ’97 Modem Controller Registers (D31:F6)
Bit
Description
Read Completion Status (RCS) — R/WC. This bit indicates the status of codec read completions.
0 = A codec read completes normally.
15 _{1 = A codec read results in a time-out. The bit remains set until being cleared by software writing a}
1 to the bit location.
This bit is not affected by D3_HOT to D0 Reset.
14 Bit 3 of slot 12 — RO. Display bit 3 of the most recent slot 12.
13 Bit 2 of slot 12 — RO. Display bit 2 of the most recent slot 12.
12 Bit 1 of slot 12 — RO. Display bit 1 of the most recent slot 12.
AC_SDIN1 Resume Interrupt (S1RI) — R/WC. This bit indicates that a resume event occurred on
AC_SDIN[1].
11 0 = Cleared by writing a 1 to this bit position.
1 = Resume event occurred.
This bit is not affected by D3_HOT to D0 Reset.
AC_SDIN0 Resume Interrupt (S0RI) — R/WC. This bit indicates that a resume event occurred on
AC_SDIN[0].
10 0 = Cleared by writing a 1 to this bit position.
1 = Resume event occurred.
This bit is not affected by D3_HOT to D0 Reset.
AC_SDIN1 Codec Ready (S1CR) — RO. Reflects the state of the codec ready bit in AC_SDIN[1].
Bus masters ignore the condition of the codec ready bits, so software must check this bit before
9
starting the bus masters. Once the codec is “ready”, it must never go “not ready” spontaneously.
0 = Not Ready.
1 = Ready.
AC_SDIN0 Codec Ready (S0CR) — RO. Reflects the state of the codec ready bit in AC_SDIN [0].
Bus masters ignore the condition of the codec ready bits, so software must check this bit before
8
starting the bus masters. Once the codec is “ready”, it must never go “not ready” spontaneously.
0 = Not Ready.
1 = Ready.
Mic In Interrupt (MINT) — RO.
7 0 = When the specific status bit is cleared, this bit will be cleared.
1 = This bit indicates that one of the Mic in channel interrupts status bits has been set.
PCM Out Interrupt (POINT) — RO.
6 0 = When the specific status bit is cleared, this bit will be cleared.
1 = This bit indicates that one of the PCM out channel interrupts status bits has been set.
PCM In Interrupt (PIINT) — RO.
5 0 = When the specific status bit is cleared, this bit will be cleared.
1 = This bit indicates that one of the PCM in channel interrupts status bits has been set.
4:3 Reserved
Modem Out Interrupt (MOINT) — RO.
2 0 = When the specific status bit is cleared, this bit will be cleared.
1 = This bit indicates that one of the modem out channel interrupts status bits has been set.
Modem In Interrupt (MIINT) — RO.
1 0 = When the specific status bit is cleared, this bit will be cleared.
1 = This bit indicates that one of the modem in channel interrupts status bits has been set.
GPI Status Change Interrupt (GSCI) — RWC.
0 = The bit is cleared by software writing a 1 to this bit location.
0 _{1 = This bit reflects the state of bit 0 in slot 12, and is set when bit 0 of slot 12 is set. This indicates}
that one of the GPIs changed state, and that the new values are available in slot 12.
This bit is not affected by D3_HOT to D0 Reset.
Intel^® 82801DB ICH4 Datasheet
509