82801DB Datasheet, PDF (576/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

Register Index
Table A-3. Intel^® ICH4 Variable I/O Registers (Sheet 4 of 6)
Register Name
Offset
Datasheet Location
Auxiliary Status
Auxiliary Control
0Ch
Section 13.2.11, “AUX_STS—Auxiliary Status Register” on page 13-461
0Dh
Section 13.2.12, “AUX_CTL—Auxiliary Control Register” on page 13-462
AC ’97 Audio I/O Registers at NAMBAR + Offset
NAMBAR is set at Section 14.1.11, “NABMBAR—Native Audio Bus Mastering Base Address Register (Audio—D31:F5)”
on page 14-473
PCM In Buffer Descriptor list
Base Address Register
00h
Section 14.2.1, “x_BDBAR—Buffer Descriptor Base Address Register” on
page 14-482
PCM In Current Index Value
04h
Section 14.2.2, “x_CIV—Current Index Value Register” on page 14-483
PCM In Last Valid Index
05h
Section 14.2.3, “x_LVI—Last Valid Index Register” on page 14-483
PCM In Status Register
06h
Section 14.2.4, “x_SR—Status Register” on page 14-484
PCM In Position In Current Buffer
08h
Section 14.2.5, “x_PICB—Position In Current Buffer Register” on
page 14-485
PCM In Prefetched Index Value
0Ah
Section 14.2.6, “x_PIV—Prefetched Index Value Register” on page 14-485
PCM In Control Register
0Bh
Section 14.2.7, “x_CR—Control Register” on page 14-486
PCM Out Buffer Descriptor list
Base Address Register
10h
Section 14.2.1, “x_BDBAR—Buffer Descriptor Base Address Register” on
page 14-482
PCM Out Current Index Value
14h
Section 14.2.2, “x_CIV—Current Index Value Register” on page 14-483
PCM Out Last Valid Index
15h
Section 14.2.3, “x_LVI—Last Valid Index Register” on page 14-483
PCM Out Status Register
16h
Section 14.2.4, “x_SR—Status Register” on page 14-484
PCM Out Position In Current
Buffer
18h
Section 14.2.5, “x_PICB—Position In Current Buffer Register” on
page 14-485
PCM Out Prefetched Index Value
1Ah
Section 14.2.6, “x_PIV—Prefetched Index Value Register” on page 14-485
PCM Out Control Register
1Bh
Section 14.2.7, “x_CR—Control Register” on page 14-486
Mic. In Buffer Descriptor list Base
Address Register
20h
Section 14.2.1, “x_BDBAR—Buffer Descriptor Base Address Register” on
page 14-482
Mic. In Current Index Value
24h
Section 14.2.2, “x_CIV—Current Index Value Register” on page 14-483
Mic. In Last Valid Index
25h
Section 14.2.3, “x_LVI—Last Valid Index Register” on page 14-483
Mic. In Status Register
26h
Section 14.2.4, “x_SR—Status Register” on page 14-484
Mic In Position In Current Buffer
28h
Section 14.2.5, “x_PICB—Position In Current Buffer Register” on
page 14-485
Mic. In Prefetched Index Value
2Ah
Section 14.2.6, “x_PIV—Prefetched Index Value Register” on page 14-485
Mic. In Control Register
2Bh
Section 14.2.7, “x_CR—Control Register” on page 14-486
Global Control
2Ch
Section 14.2.8, “GLOB_CNT—Global Control Register” on page 14-487
Global Status
30h
Section 14.2.9, “GLOB_STA—Global Status Register” on page 14-488
Codec Access Semaphore
Register
34h
Section 14.2.10, “CAS—Codec Access Semaphore Register” on
page 14-490
AC ’97 Audio I/O Registers at MBBAR + Offset
MBBAR is set at Section 14.1.13, “MBBAR—Bus Master Base Address Register (Audio—D31:F5)” on page 14-474
Mic. 2 Buffer Descriptor list Base
Address Register
Mic. 2 Current Index Value
40–43h
44h
Section 14.2.1, “x_BDBAR—Buffer Descriptor Base Address Register” on
page 14-482
Section 14.2.2, “x_CIV—Current Index Value Register” on page 14-483
576
Intel^® 82801DB ICH4 Datasheet