82801DB Datasheet, PDF (302/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

LPC Interface Bridge Registers (D31:F0)
9.1.22
GEN_CNTL — General Control Register (LPC I/F — D31:F0)
Offset Address:
Default Value:
Lockable:
D0h–D3h
00000000h
No
Attribute:
Size:
Power Well:
R/W
32 bit
Core
Bit
Description
31:26
25
24
23:22
21
20
19:18
17:14
13
12
11
10:9
Reserved
REQ[5]#/GNT[5]# PC/PCI Protocol Select (PCPCIB_SEL) — R/W.
0 = REQ[5]#/GNT[5]# pins function as a standard PCI REQ/GNT signal pair.
1 = PCI REQ[5]#/GNT[5]# signal pair use the PC/PCI protocol as REQ[B]#/GNT[B]. The
corresponding bits in the GPIO_USE_SEL register must also be set to a 0. If the corresponding
bits in the GPIO_USE_SEL register are set to a 1, then the signals will be used as a GPI and
GPO.
Hide ISA Bridge (HIDE_ISA) — R/W.
0 = The Intel^® ICH4 does not prevent AD22 from asserting during configuration cycles to the PCI-
to-ISA bridge.
1 = Software sets this bit to 1 to disable configuration cycle from being claimed by a PCI-to-ISA
bridge. This prevents the OS PCI PnP from getting confused by seeing two ISA bridges.
It is required for the ICH4 PCI address line AD22 to connect to the PCI-to-ISA bridge’s IDSEL
input. When this bit is set, the ICH4 will not assert AD22 during configuration cycles to the PCI-
to-ISA bridge.
Reserved
CPU Break Event Indication Enable (FERR#-MUX-EN) — R/W.
0 = Disable. The ICH4 does not examine the FERR# signal during C2. (Default)
1 = Enables the ICH4 to examine the FERR# signal during a C2 state as a break event. (See
Section 5.12.5 for details.)
Reserved
SCRATCHPAD. These bits are provided for possible future use.
Reserved
Coprocessor Error Enable (COPR_ERR_EN) — R/W.
0 = FERR# will not generate IRQ13 nor IGNNE#.
1 = When FERR# is low, ICH4 generates IRQ13 internally and holds it until an I/O write to port F0h.
It will also drive IGNNE# active.
Keyboard IRQ1 Latch Enable (IRQ1LEN) — R/W.
0 = IRQ1 bypasses the latch.
1 = The active edge of IRQ1 is latched and held until a port 60h read.
Mouse IRQ12 Latch Enable (IRQ12LEN) — R/W.
0 = IRQ12 bypasses the latch.
1 = The active edge of IRQ12 is latched and held until a port 60h read.
Reserved
302
Intel^® 82801DB ICH4 Datasheet