82801DB Datasheet, PDF (180/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

Functional Description
5.16.2.3 Command Register, Status Register, and TD Status Bit Interaction
Table 5-64. Command Register, Status Register, and TD Status Bit Interaction
Condition
Intel^® ICH4 USB Status Register Actions
TD Status Register Actions
CRC/Time Out Error
Set USB Error Int bit¹, Clear HC Halted bit Clear Active bit¹ and set Stall bit¹
Illegal PID, PID Error,
Max Length (illegal)
Clear Run/Stop bit in Command register
Set HC Process Error and HC Halted bits
PCI Master/Target Abort
Suspend Mode
Clear Run/Stop bit in Command register
Set Host System Error and HC Halted bits
Clear Run/Stop bit in Command register²
Set HC Halted bit
Resume Received and
Suspend Mode = 1
Set Resume received bit
Run/Stop = 0
Clear Run/Stop bit in command register
Set HC Halted bit
Configuration Flag Set
Set Configuration Flag in Command
register
HC Reset/Global Reset
Clear Run/Stop and Configuration Flag in
Command register
Clear USB Int, USB Error Int, Resume
received, Host System Error, HC Process
Error, and HC Halted bits
IOC = 1 in TD Status
Set USB Int bit
Stall
Set USB Error Int bit
Bit Stuff/Data Buffer Error Set USB Error Int bit¹
Clear Active bit¹ and set Stall bit
Clear Active bit¹ and set Stall bit¹
Short Packet Detect
Set USB Int bit
Clear Active bit
NOTES:
1. Only If error counter counted down from 1 to 0
2. Suspend mode can be entered only when Run/Stop bit is 0
Note that if a NAK or STALL response is received from a SETUP transaction, a Time Out Error
will be reported. This causes the Error counter to decrement and the CRC/Time-out Error status bit
to be set within the TD Control and Status DWord during write back. If the Error counter changes
from 1 to 0, the Active bit is reset to 0 and Stalled bit to 1 as normal.
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Intel^® 82801DB ICH4 Datasheet