82801DB Datasheet, PDF (254/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

LAN Controller Registers (B1:D8:F0)
7.1.4
PCISTS—PCI Status Register (LAN Controller—B1:D8:F0)
Offset Address: 06–07h
Default Value: 0290h
Attribute:
Size:
R/WC, RO
16 bits
Bit
Description
Detected Parity Error (DPE) — R/WC.
15 ^{0 = This bit is cleared by writing a 1 to the bit location.}
1 = The Intel^® ICH4’s integrated LAN controller has detected a parity error on the PCI bus (will be
set even if Parity Error Response is disabled in the PCI Command register).
Signaled System Error (SSE) — R/WC.
14 ^{0 = This bit is cleared by writing a 1 to the bit location.}
1 = The ICH4’s integrated LAN controller has asserted SERR#. (SERR# can be routed to cause
NMI, SMI# or interrupt.
Master Abort Status (MAS) — R/WC.
13 0 = This bit is cleared by writing a 1 to the bit location.
1 = The ICH4’s integrated LAN controller (as a PCI master) has generated a master abort.
Received Target Abort (RTA) — R/WC.
12 0 = This bit is cleared by writing a 1 to the bit location.
1 = The ICH4’s integrated LAN controller (as a PCI master) has received a target abort.
11 Signaled Target Abort (STA) — RO. Hardwired to 0. The device will never signal Target Abort.
DEVSEL# Timing Status (DEV_STS) —RO.
10:9
01h = Medium timing.
Data Parity Error Detected (DPED) — R/WC.
0 = This bit is cleared by writing a 1 to the bit location.
8 ^{1 = All of the following three conditions have been met:}
1. The LAN controller is acting as bus master
2. The LAN controller has asserted PERR# (for reads) or detected PERR# asserted (for writes)
3. The Parity Error Response bit in the LAN controller’s PCI Command Register is set.
7
Fast Back to Back Capable (FB2BC) — RO. Hardwired to 1. The device can accept fast back-to-
back transactions.
6 User Definable Features (UDF) — RO. Hardwired to 0. Not implemented.
5 66 MHz Capable (66MHZ_CAP) — RO. Hardwired to 0. The device does not support 66 MHz PCI.
Capabilities List (CAP_LIST) — RO.
4
0 = The EEPROM indicates that the integrated LAN controller does not support PCI Power
Management.
1 = The EEPROM indicates that the integrated LAN controller supports PCI Power Management.
3:0 Reserved
254
Intel^® 82801DB ICH4 Datasheet