82801DB Datasheet, PDF (413/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

USB UHCI Controllers Registers
11.2.5
FRBASEADD—Frame List Base Address
I/O Offset:
Default Value:
Base + (08–0Bh)
Undefined
Attribute:
Size:
R/W
32 bits
This 32-bit register contains the beginning address of the Frame List in the system memory. HCD
loads this register prior to starting the schedule execution by the Host controller. When written,
only the upper 20 bits are used. The lower 12 bits are written as 0s (4-KB alignment). The contents
of this register are combined with the frame number counter to enable the Host controller to step
through the Frame List in sequence. The two least significant bits are always 00. This requires
DWord alignment for all list entries. This configuration supports 1024 Frame List entries.
Bit
31:12
11:0
Description
Base Address — R/W. These bits correspond to memory address signals [31:12], respectively.
Reserved
Intel^® 82801DB ICH4 Datasheet
413