82801DB Datasheet, PDF (312/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

LPC Interface Bridge Registers (D31:F0)
9.1.35
FWH_DEC_EN2—FWH Decode Enable 2 Register
(LPC I/F—D31:F0)
Offset Address: F0h
Default Value: 0Fh
Attribute:
Size:
R/W
8 bits
This register determines which memory ranges will be decoded on the PCI bus and forwarded to
the FWH. The ICH4 will subtractively decode cycles on PCI unless POS_DEC_EN is set to 1.
Bit
Description
7:4 Reserved
FWH_70_EN — R/W. Enables decoding two 1M FWH memory ranges.
0 = Disable.
3
1 = Enable the following ranges for the FWH
FF70 0000h–FF7F FFFFh
FF30 0000h–FF3F FFFFh
FWH_60_EN — R/W. Enables decoding two 1M FWH memory ranges.
0 = Disable.
2
1 = Enable the following ranges for the FWH
FF60 0000h–FF6F FFFFh
FF20 0000h–FF2F FFFFh
FWH_50_EN — R/W. Enables decoding two 1M FWH memory ranges.
0 = Disable.
1
1 = Enable the following ranges for the FWH
FF50 0000h–FF5F FFFFh
FF10 0000h–FF1F FFFFh
FWH_40_EN — R/W. Enables decoding two 1M FWH memory ranges.
0 = Disable.
0
1 = Enable the following ranges for the FWH
FF40 0000h–FF4F FFFFh
FF00 0000h–FF0F FFFFh
312
Intel^® 82801DB ICH4 Datasheet