82801DB Datasheet, PDF (365/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

LPC Interface Bridge Registers (D31:F0)
9.8.3.10
SMI_STS—SMI Status Register
I/O Address:
Default Value:
Lockable:
Power Well:
PMBASE + 34h
0000h
No
Core
Attribute:
Size:
Usage:
R/WC, RO
32-bit
ACPI or Legacy
Note:
If the corresponding _EN bit is set when the _STS bit is set, the ICH4 will cause an SMI# (except
bits 8:10 and 12, which don’t need enable bits since they are logic ORs of other registers that have
enable bits). The ICH4 uses the same GPE0_EN register (I/O address: PMBase+2Ch) to enable/
disable both SMI and ACPI SCI general purpose input events. ACPI OS assumes that it owns the
entire GPE0_EN register per ACPI spec. Problems arise when some of the general-purpose inputs
are enabled as SMI by BIOS, and some of the general purpose inputs are enabled for SCI. In this
case ACPI OS turns off the enabled bit for any GPIx input signals that are not indicated as SCI
general-purpose events at boot, and exit from sleeping states. BIOS should define a dummy control
method which prevents the ACPI OS from clearing the SMI GPE0_EN bits.
Bit
Description
31:19 Reserved
INTEL_USB2_STS — RO. This non-sticky read-only bit is a logical OR of each of the SMI status bits
18 in the Intel-Specific USB EHCI SMI Status Register ANDed with the corresponding enable bits. This
bit will not be active if the enable bits are not set. Writes to this bit have no effect.
LEGACY_USB2_STS — RO. This non-sticky read-only bit is a logical OR of each of the SMI status
17 bits in the USB EHCI Legacy Support Register ANDed with the corresponding enable bits. This bit will
not be active if the enable bits are not set. Writes to this bit will have no effect.
SMBus SMI Status (SMBUS_SMI_STS) — R/WC.
0 = This bit is cleared by writing a 1 to its bit position. This bit is set from the 64 KHz clock domain
used by the SMBus. Software must wait at least 15.63 us after the initial assertion of this bit
before clearing it.
1 = Indicates that the SMI# was caused by:
16
• The SMBus Slave receiving a message, or
• The SMBALERT# signal goes active and the SMB_SMI_EN bit is set and the
SMBALERT_DIS bit is cleared, or
• The SMBus Slave receiving a Host Notify message and the HOST_NOTIFY_INTREN and
the SMB_SMI_EN bits are set, or
• The Intel^® ICH4 detecting the SMLINK_SLAVE_SMI command while in the S0 state.
SERIRQ_SMI_STS — RO.
15 0 = SMI# was not caused by SERIRQ decoder. This is not a sticky bit.
1 = SMI# was caused by the SERIRQ decoder.
PERIODIC_STS — R/WC.
14
• This bit is cleared by writing a 1 to its bit position.
1 = This bit will be set at the rate determined by the PER_SMI_SEL bits. If the PERIODIC_EN bit is
also set, the ICH4 will generate an SMI#.
TCO_STS — RO.
13 0 = SMI# not caused by TCO logic.
1 = SMI# was caused by the TCO logic. Note that this is not a wake event.
Intel^® 82801DB ICH4 Datasheet
365