82801DB Datasheet, PDF (271/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

LAN Controller Registers (B1:D8:F0)
7.2.10
Power Management Driver (PMDR) Register
Offset Address: 1Bh
Default Value: 00h
Attribute:
Size:
R/WC
8 bits
The ICH4’s internal LAN controller provides an indication in the PMDR that a wake-up event has
occurred.
Bit
Description
Link Status Change Indication — R/WC.
7 0 = Software clears this bit by writing a 1 to the bit location
1 = The link status change bit is set following a change in link status.
Magic Packet — R/WC.
0 = Software clears this bit by writing a 1 to the bit location.
6
1 = This bit is set when a Magic Packet is received regardless of the Magic Packet wake-up disable
bit in the configuration command and the PME Enable bit in the Power Management Control/
Status Register.
Interesting Packet — R/WC.
5
0 = Software clears this bit by writing a 1 to the bit location.
1 = This bit is set when an “interesting” packet is received. Interesting packets are defined by the
LAN controller packet filters.
4:1 Reserved
PME Status — R/WC. This bit is a reflection of the PME Status bit in the Power Management
Control/Status Register (PMCSR).
0 0 = Software clears this bit by writing a 1 to the bit location. This also clears the PME Status bit in
the PMCSR and de-asserts the PME signal.
1 = Set upon a wake-up event, independent of the PME Enable bit.
Intel^® 82801DB ICH4 Datasheet
271