82801DB Datasheet, PDF (195/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

Functional Description
5.17 USB EHCI Controller (D29:F7)
The ICH4 contains an Enhanced Host Controller Interface (EHCI) compliant host controller which
supports up to six, high-speed USB 2.0 Specification compliant root ports. High-speed USB 2.0
allows data transfers up to 480 Mbps using the same pins as the 6 Full-speed/Low-speed USB
UHCI ports. The ICH4 contains port-routing logic that determines whether a USB port is
controlled by one of the UHCI controllers or by the EHCI controller. A USB 2.0 based Debug Port
is also implemented in the ICH4.
A summary of the key architectural differences between the USB UHCI host controllers and the
USB EHCI host controller are shown in Table 5-66.
Table 5-76. UHCI vs. EHCI
Accessible by
Memory Data Structure
Differential Signaling Voltage
Ports per Controller
USB UHCI
I/O space
Single linked list
3.3 V
2
USB EHCI
Memory Space
Separated in to Periodic and Asynchronous lists
400 mV
6
5.17.1
5.17.1.1
5.17.1.2
EHC Initialization
The following descriptions step through the expected ICH4 Enhanced Host Controller (EHC)
initialization sequence in chronological order, beginning with a complete power cycle in which the
suspend well and core well have been off.
Power On
The suspend well is a “deeper” power plane than the core well, which means that the suspend well
is always functional when the core well is functional but the core well may not be functional when
the suspend well is. Therefore, the suspend well reset pin (RSMRST#) deasserts before the core
well reset pin (PWROK) rises.
1. The suspend well reset deasserts, leaving all registers and logic in the suspend well in the
default state. However, it is not possible to read any registers until after the core well reset
deasserts. Note that normally the suspend well reset will only occur when a system is
unplugged. In other words, suspend well resets are not easily achieved by software or the end-
user. This step will typically not occur immediately before the remaining steps.
2. The core well reset deasserts, leaving all registers and logic in the core well in the default state.
The EHC configuration space is accessible at this point. Note that the core well reset can (and
typically does) occur without the suspend well reset asserting. This means that all of the
Configure Flag and Port Status and Control bits (and any other suspend-well logic) may be in
any valid state at this time.
BIOS Initialization
BIOS performs a number of platform customization steps after the core well has powered up.
Contact your intel field sales representative for the latest BIOS information.
Intel^® 82801DB ICH4 Datasheet
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