82801DB Datasheet, PDF (382/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

LPC Interface Bridge Registers (D31:F0)
9.10.7
GP_IO_SEL2—GPIO Input/Output Select 2 Register
Offset Address:
Default Value:
Lockable:
GPIOBASE +34h
00000000h
No
Attribute:
Size:
Power Well:
R/W
32-bit
Core
9.10.8
Bit
31:12
11:0
Description
Always 0. No corresponding GPIO.
GP_IO_SEL2[43:32] — R/W. When set to a 1, the corresponding GPIO signal (if enabled in the
GPIO_USE_SEL2 register) is programmed as an input. When set to 0, the GPIO signal is
programmed as an output.
GP_LVL2—GPIO Level for Input or Output 2 Register
Offset Address:
Default Value:
Lockable:
GPIOBASE +38h
00000FFFh
No
Attribute:
Size:
Power Well:
R/W
32-bit
See below
Bit
31:12
11:0
Description
Reserved. Read-only 0
GP_LVL2[43:32] — R/W. If GPIO[n] is programmed to be an output (via the corresponding bit
in the GP_IO_SEL2 register), then the corresponding GP_LVL2[n] bit can be updated by
software to drive a high or low value on the output pin. 1 = high, 0 = low. If GPIO[n] is
programmed as an input, then the corresponding GP_LVL2 bit reflects the state of the input
signal (1 = high, 0 = low). Writes will have no effect.
Since these bits correspond to GPIO that are in the core well, these bits will be reset by
PCIRST#.
382
Intel^® 82801DB ICH4 Datasheet