82801DB Datasheet, PDF (346/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

LPC Interface Bridge Registers (D31:F0)
9.8.1.1
GEN_PMCON_1—General PM Configuration 1 Register (PM—D31:F0)
Offset Address: A0h
Default Value: 00h
Lockable:
No
Attribute:
Size:
Usage:
Power Well:
R/W, RO, R/WO, R/WC
16 bit
ACPI, Legacy
Core
Bit
15:11
10
9
8:7
6
5
4
3:2
1:0
Description
Reserved
Reserved
PWRBTN_LVL — RO. This read-only bit indicates the current state of the PWRBTN# signal.
0 = Low.
1 = High.
Reserved
64_EN. Software sets this bit to indicate that the processor is an IA_64 processor, not an IA_32
processor.This may be used in various state machines where there are behavioral differences.
CPU SLP# Enable (CPUSLP_EN) — R/W.
0 = Disable.
1 = Enables the CPUSLP# signal to go active in the S1 states. This reduces the CPU power.
Note that CPUSLP# will go active on entry to S3, S4 and S5 even if this bit is not set.
SMI_LOCK — R/W-Once. When this bit is set, writes to the GLB_SMI_EN bit will have no effect.
Once the SMI_LOCK bit is set, writes of 0 to SMI_LOCK bit will have no effect (i.e., once set, this
bit can only be cleared by PCIRST#).
Reserved
Periodic SMI# Rate Select (PER_SMI_SEL) — R/W. Set by software to control the rate the
periodic SMI# is generated.
00 = 1 minute
01 = 32 seconds
10 = 16 seconds
11 = 8 seconds
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Intel^® 82801DB ICH4 Datasheet