82801DB Datasheet, PDF (490/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

AC ’97 Audio Controller Registers (D31:F5)
Bit
Description
AC_SDIN0 Codec Ready (S0CR) — RO. This bit reflects the state of the codec ready bit in
AC_SDIN [0]. Bus masters ignore the condition of the codec ready bits, so software must check this
bit before starting the bus masters. Once the codec is “ready”, it must never go “not ready”
8 _{spontaneously.}
0 = Not Ready.
1 = Ready.
Mic In Interrupt (MINT) — RO.
7 0 = When the specific status bit is cleared, this bit will be cleared.
1 = This bit indicates that one of the Mic in channel interrupts status bits has been set.
PCM Out Interrupt (POINT) — RO.
6 0 = When the specific status bit is cleared, this bit will be cleared.
1 = This bit indicates that one of the PCM out channel interrupts status bits has been set.
PCM In Interrupt (PIINT) — RO.
5 0 = When the specific status bit is cleared, this bit will be cleared.
1 = This bit indicates that one of the PCM in channel interrupts status bits has been set.
4:3 Reserved
Modem Out Interrupt (MOINT) — RO.
2 0 = When the specific status bit is cleared, this bit will be cleared.
1 = This bit indicates that one of the modem out channel interrupts status bits has been set.
Modem In Interrupt (MIINT) — RO.
1 0 = When the specific status bit is cleared, this bit will be cleared.
1 = This bit indicates that one of the modem in channel interrupts status bits has been set.
GPI Status Change Interrupt (GSCI) — R/WC.
0 = The bit is cleared by software writing a 1 to this bit location.
0 _{1 = This bit reflects the state of bit 0 in slot 12, and is set when bit 0 of slot 12 is set. This indicates}
that one of the GPIs changed state, and that the new values are available in slot 12.
This bit is not affected by D3_HOT to D0 Reset.
14.2.10
CAS—Codec Access Semaphore Register
I/O Address:
Default Value:
Lockable:
NABMBAR + 34h
00h
No
Attribute:
Size:
Power Well:
Reads across DWord boundaries are not supported.
R/W
8 bits
Core
Bit
Description
7:1 Reserved.
Codec Access Semaphore (CAS) — R/W-Special. This bit is read by software to check whether a
codec access is currently in progress.
0 0 = No access in progress.
1 = The act of reading this register sets this bit to 1. The driver that read this bit can then perform
an I/O access. Once the access is completed, hardware automatically clears this bit.
490
Intel^® 82801DB ICH4 Datasheet