82801DB Datasheet, PDF (500/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

AC ’97 Modem Controller Registers (D31:F6)
15.1.18
PC—Power Management Capabilities Register
(Modem—D31:F6)
Address Offset:
Default Value:
Lockable:
52h
C9C2h
No
Attribute:
Size:
Power Well:
RO
16 bits
Core
Bit
Description
15:11 PME Support — RO. This field indicates PME# can be generated from all D states.
10:9 Reserved.
8:6
Auxiliary Current — RO. This field reports 375 mA maximum Suspend well current required when in
the D3cold state.
5
Device Specific Initialization (DSI) — RO. This bit indicates that no device-specific initialization is
required.
4 Reserved — RO.
3 PME Clock — RO. This bit indicates that PCI clock is not required to generate PME#.
2:0
Version — RO. This field indicates support for Revision 1.1 of the PCI Power Management
Specification.
15.1.19
PCS—Power Management Control and Status Register
(Modem—D31:F6)
Address Offset:
Default Value:
Lockable:
54h
0000h
No
Attribute:
Size:
Power Well:
This register is not affected by the D3_HOT to D0 transition.
R/W, R/WC
16 bits
Resume
Bit
Description
PME Status (PMES) — RW/C.
15 ^{0 = Software clears this bit by writing a 1 to the bit position.}
1 = This bit is set when the AC ’97 controller would normally assert the PME# signal independent of
the state of the PME_En bit. This bit resides in the resume well.
14:9 Reserved — RO.
8
PME Enable (PMEE) — R/W. When set, and if corresponding PMES is also set, the AC'97 controller
sets the AC97_STS bit in the GPE0_STS register
7:2 Reserved — RO.
Power State — R/W. This field is used both to determine the current power state of the AC ’97
controller and to set a new power state. The values are:
00 = D0 state
01 = not supported
1:0 ^{10 = not supported}
11 = D3_HOT state
When in the D3_HOT state, the AC ’97 controller’s configuration space is available, but the I/O and
memory spaces are not. Additionally, interrupts are blocked.
If software attempts to write a value of 10b or 01b in to this field, the write operation must complete
normally; however, the data is discarded and no state change occurs.
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Intel^® 82801DB ICH4 Datasheet