82801DB Datasheet, PDF (224/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

Functional Description
.
Table 5-95. Command Types
Command
Type
0
1
2
3
4
5
6
7
8
9–FFh
Description
Reserved
WAKE/SMI#: Wake system if it is not already awake. If system is already awake, then an
SMI# will be generated.
NOTE: The SMB_WAK_STS bit will be set by this command, even if the system is already
awake. The SMI handler should then clear this bit.
Unconditional Powerdown: This command sets the PWRBTNOR_STS bit, and has the
same effect as the Powerbutton Override occurring.
HARD RESET WITHOUT CYCLING: The will cause a hard reset of the system (does not
include cycling of the power supply). This is equivalent to a write to the CF9h register with
bits 2:1 set to 1, but bit 3 set to 0.
HARD RESET SYSTEM: The will cause a hard reset of the system (including cycling of the
power supply). This is equivalent to a write to the CF9h register with bits 3:1 set to 1.
Disable the TCO Messages: This command will disable the Intel^® ICH4 from sending
Heartbeat and Event messages (as described in Section 5.13.2). Once this command has
been executed, Heartbeat and Event message reporting can only be re-enabled by
assertion and deassertion of the RSMRST# signal.
WD RELOAD: Reload watchdog timer.
Reserved
SMLINK_SLV_SMI: When ICH4 detects this command type while in the S0 state, it sets the
SMLINK_SLV_SMI_STS bit (see Section 9.9.7). This command should only be used if the
system is in an S0 state. If the message is received during S1–S5 states, the ICH4
acknowledges it, but the SMLINK_SLV_SMI_STS bit does not get set.
NOTE: It is possible that the system transitions out of the S0 state at the same time that the
SMLINK_SLV_SMI command is received. In this case, the SMLINK_SLV_SMI_STS
bit may get set but not serviced before the system goes to sleep. Once the system
returns to S0, the SMI associated with this bit would then be generated. Software
must be able to handle this scenario.
Reserved
5.18.7.2
Format of Read Command
The external master performs Byte Read commands to the ICH4 SMBus Slave interface. The
“Command” field (bits 11–18) indicate which register is being accessed. The Data field (bits 30-
37) contain the value that should be read from that register. Table 5-96 shows the Read Cycle
format. Table 5-97 shows the register mapping for the data byte.
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Intel^® 82801DB ICH4 Datasheet