82801DB Datasheet, PDF (470/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

AC ’97 Audio Controller Registers (D31:F5)
14.1.4
PCISTS—PCI Device Status Register (Audio—D31:F5)
Offset:
Default Value
Lockable:
06–07h
0280h
No
Attribute:
Size:
Power Well:
R/WC, RO
16 bits
Core
PCISTA is a 16-bit status register. Refer to the PCI 2.2 specification for complete details on each
bit.
Bit
Description
15 Detected Parity Error (DPE) — RO. Not implemented. Hardwired to 0.
14 Signaled System Error (SSE) — RO. Not implemented. Hardwired to 0.
Master Abort Status (MAS) — R/WC.
13 0 = Software clears this bit by writing a 1 to the bit position.
1 = Bus Master AC '97 2.3 interface function, as a master, generates a master abort.
12 Reserved. Will always read as 0.
11 Signaled Target Abort (STA) — RO. Not implemented. Hardwired to 0.
DEVSEL# Timing Status (DEV_STS) — RO. This 2-bit field reflects the ICH4's DEVSEL# timing
10:9 ^{when performing a positive decode.}
01b = Medium timing.
8
Data Parity Error Detected (DPED) — RO. Not implemented. Hardwired to 0.
7
Fast Back to Back Capable (FB2BC) — RO. Hardwired to 1. This bit indicates that the ICH4 as a
target is capable of fast back-to-back transactions.
6
User Definable Features (UDF) — RO. Not implemented. Hardwired to 0.
5
66 MHz Capable (66MHZ_CAP) — RO. Hardwired to 0.
4
Capabilities List (CLIST) — RO. Indicates that the controller contains a capabilities pointer list. The
first item is pointed to by looking at configuration offset 34h.
3:0 Reserved.
470
Intel^® 82801DB ICH4 Datasheet