82801DB Datasheet, PDF (72/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

Functional Description
5.1.7
5.2
PCI Dual Address Cycle (DAC) Support
The ICH4 supports Dual Address Cycle (DAC) format on PCI for cycles from PCI initiators to
main memory. This allows PCI masters to generate an address up to 44 bits. The size of the actual
supported memory space will be determined by the Memory controller and the processor.
The DAC mode is only supported for PCI adapters and USB EHCI, and is not supported for any of
the internal PCI masters (IDE, LAN, USB UHCI, AC ’97, 8237 DMA, etc.).
When a PCI master wants to initiate a cycle with an address above 4 GB, it follows the following
behavioral rules (See PCI Local Bus Specification, Revision 2.2, Section 3.9 for more details):
1. On the first clock of the cycle (when FRAME# is first active), the peripheral uses the DAC
encoding on the C/BE# signals. This unique encoding is: 1101.
2. Also during the first clock, the peripheral drives the AD[31:0] signals with the low address.
3. On the second clock, the peripheral drives AD[31:0] with the high address. The address is
right justified: A[43:32] appear on AD[12:0]. The value of AD[31:13] is expected to be 0,
however the ICH4 will ignore these bits. C/BE# indicate the bus command type (Memory
Read, Memory Write, etc.)
4. The rest of the cycle proceeds normally.
LAN Controller (B1:D8:F0)
The ICH4’s integrated LAN controller includes a 32-bit PCI controller that provides enhanced
scatter-gather bus mastering capabilities and enables the LAN controller to perform high-speed
data transfers over the PCI bus. Its bus master capabilities enable the component to process high
level commands and perform multiple operations, which lowers processor utilization by off-
loading communication tasks from the processor. Two large transmit and receive FIFOs of 3 KB
each help prevent data underruns and overruns while waiting for bus accesses. This enables the
integrated LAN controller to transmit data with minimum interframe spacing (IFS).
The ICH4 integrated LAN controller can operate in either full-duplex or half-duplex mode. In full-
duplex mode the LAN controller adheres with the IEEE 802.3x Flow Control specification. Half
duplex performance is enhanced by a proprietary collision reduction mechanism.
The integrated LAN controller also includes an interface to a serial (4-pin) EEPROM. The
EEPROM provides power-on initialization for hardware and software configuration parameters.
From a software perspective, the integrated LAN controller appears to reside on the secondary side
of the ICH4’s virtual PCI-to-PCI Bridge (see Section 5.1.2). This is typically Bus 1, but may be
assigned a different number, depending on system configuration.
The following summarizes the ICH4 LAN controller features:
• Compliance with Advanced Configuration and Power Interface and PCI Power Management
standards
• Support for wake-up on interesting packets and link status change
• Support for remote power-up using Wake on LAN (WOL) technology
• Deep power-down mode support
• Support of Wired for Management (WfM) Rev 2.0
• Backward compatible software with 82557, 82558 and 82559
• TCP/UDP checksum off load capabilities
• Support for Intel’s Adaptive Technology
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Intel^® 82801DB ICH4 Datasheet