82801DB Datasheet, PDF (455/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

SMBus Controller Registers (D31:F3)
13.1.13 HOSTC—Host Configuration Register (SMBUS—D31:F3)
Address Offset: 40h
Default Value: 00h
Attribute:
Size:
R/W
8 bits
Bit
Description
7:3 Reserved
I²C_EN — R/W.
2
0 = SMBus behavior.
1 = The ICH4 is enabled to communicate with I²C devices. This will change the formatting of some
commands.
SMB_SMI_EN — R/W. This bit needs to be set for SMBALERT# to be enabled.
1
0 = SMBus interrupts will not generate an SMI#.
1 = Any source of an SMB interrupt will instead be routed to generate an SMI#. Refer to
Section 5.18.4 (Interrupts / SMI#).
SMBus Host Enable (HST_EN) — R/W.
0 = Disable the SMBus Host controller.
0
1 = Enable. The SMB Host controller interface is enabled to execute commands. The INTREN bit
needs to be enabled for the SMB Host controller to interrupt or SMI#. Note that the SMB Host
controller will not respond to any new requests until all interrupt requests have been cleared.
Intel^® 82801DB ICH4 Datasheet
455