82801DB Datasheet, PDF (256/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

LAN Controller Registers (B1:D8:F0)
7.1.9
PMLT—PCI Master Latency Timer Register
(LAN Controller—B1:D8:F0)
Offset Address: 0Dh
Default Value: 00h
Attribute:
Size:
R/W
8 bits
Bit
Description
7:3
Master Latency Timer Count (MLTC) — R/W. Defines the number of PCI clock cycles that the
integrated LAN controller may own the bus while acting as bus master.
2:0 Reserved
7.1.10 HEADTYP—Header Type Register
(LAN Controller—B1:D8:F0)
Offset Address: 0Eh
Default Value: 00h
Attribute:
Size:
RO
8 bits
Bit
Description
7 Multi-Function Device — RO. Hardwired to 0 to indicate a single function device.
6:0
Header Type — RO. This 7-bit field identifies the header layout of the configuration space as an
Ethernet controller.
7.1.11 CSR_MEM_BASE CSR — Memory-Mapped Base Address
Register (LAN Controller—B1:D8:F0)
Offset Address: 10–13h
Default Value: 0000 0008h
Attribute:
Size:
R/W, RO
32 bits
Note: The ICH4’s integrated LAN controller requires one BAR for memory mapping. Software
determines which BAR (memory or I/O) is used to access the Lan controller’s CSR registers.
Bit
Description
31:12
Base Address — R/W. Upper 20 bits of the base address provides 4 KB of memory-Mapped space
for the LAN controller’s Control/Status Registers.
11:4 Reserved
3
Prefetchable — RO. Hardwired to 0 to indicate that this is not a pre-fetchable memory-Mapped
address range.
2:1
Type — RO. Hardwired to 00b to indicate the memory-Mapped address range may be located
anywhere in 32-bit address space.
0
Memory Space Indicator — RO. Hardwired to 0 to indicate that this base address maps to memory
space.
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Intel^® 82801DB ICH4 Datasheet