82801DB Datasheet, PDF (394/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

IDE Controller Registers (D31:F1)
10.1.23 SDMA_TIM—Synchronous DMA Timing Register
(IDE—D31:F1)
Address Offset: 4A–4Bh
Default Value: 0000h
Attribute: R/W
Size:
16 bits
Note: For FAST_SCB1=1 (133 MHz clk) in bits [13:12, 9:8, 5:4, 1:0], refer to Section 5.15.6 for details.
Bit
Description
15:14
13:12
11:10
9:8
7:6
5:4
3:2
1:0
Reserved
Secondary Drive 1 Cycle Time (SCT1) — R/W. For Ultra ATA mode. The setting of these bits
determines the minimum write strobe cycle time (CT). The DMARDY#-to-STOP (RP) time is also
determined by the setting of these bits.
SCB1 = 0 (33 MHz clk)
SCB1 = 1 (66 MHz clk)
FAST_SCB1 = 1 (133 MHz clk)
00 = CT 4 clocks, RP 6 clocks 00 = Reserved
00 = Reserved
01 = CT 3 clocks, RP 5 clocks 01 = CT 3 clocks, RP 8 clocks 01 = CT 3 clks, RP 16 clks
10 = CT 2 clocks, RP 4 clocks 10 = CT 2 clocks, RP 8 clocks 10 = Reserved
11 = Reserved
11 = Reserved
11 = Reserved
Reserved
Secondary Drive 0 Cycle Time (SCT0) — R/W. For Ultra ATA mode. The setting of these bits
determines the minimum write strobe cycle time (CT). The DMARDY#-to-STOP (RP) time is also
determined by the setting of these bits.
SCB1 = 0 (33 MHz clk)
SCB1 = 1 (66 MHz clk)
FAST_SCB1 = 1 (133 MHz clk)
00 = CT 4 clocks, RP 6 clocks 00 = Reserved
00 = Reserved
01 = CT 3 clocks, RP 5 clocks 01 = CT 3 clocks, RP 8 clocks 01 = CT 3 clks, RP 16 clks
10 = CT 2 clocks, RP 4 clocks 10 = CT 2 clocks, RP 8 clocks 10 = Reserved
11 = Reserved
11 = Reserved
11 = Reserved
Reserved
Primary Drive 1 Cycle Time (PCT1) — R/W. For Ultra ATA mode, the setting of these bits
determines the minimum write strobe cycle time (CT). The DMARDY#-to-STOP (RP) time is also
determined by the setting of these bits.
PCB1 = 0 (33 MHz clk)
PCB1 = 1 (66 MHz clk)
FAST_PCB1 = 1 (133 MHz clk)
00 = CT 4 clocks, RP 6 clocks 00 = Reserved
00 = Reserved
01 = CT 3 clocks, RP 5 clocks 01 = CT 3 clocks, RP 8 clocks 01 = CT 3 clks, RP 16 clks
10 = CT 2 clocks, RP 4 clocks 10 = CT 2 clocks, RP 8 clocks 10 = Reserved
11 = Reserved
11 = Reserved
11 = Reserved
Reserved
Primary Drive 0 Cycle Time (PCT0) — R/W. For Ultra ATA mode, the setting of these bits
determines the minimum write strobe cycle time (CT). The DMARDY#-to-STOP (RP) time is also
determined by the setting of these bits.
PCB1 = 0 (33 MHz clk)
PCB1 = 1 (66 MHz clk)
FAST_PCB1 = 1 (133 MHz clk)
00 = CT 4 clocks, RP 6 clocks 00 = Reserved
00 = Reserved
01 = CT 3 clocks, RP 5 clocks 01 = CT 3 clocks, RP 8 clocks 01 = CT 3 clks, RP 16 clks
10 = CT 2 clocks, RP 4 clocks 10 = CT 2 clocks, RP 8 clocks 10 = Reserved
11 = Reserved
11 = Reserved
11 = Reserved
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Intel^® 82801DB ICH4 Datasheet