82801DB Datasheet, PDF (503/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

AC ’97 Modem Controller Registers (D31:F6)
15.2.1
15.2.2
x_BDBAR—Buffer Descriptor List Base Address Register
I/O Address:
Default Value:
Lockable:
MBAR + 00h (MIBDBAR),
MBAR + 10h (MOBDBAR)
00000000h
No
Attribute:
Size:
Power Well:
R/W
32 bits
Core
Software can read the register at offset 00h by performing a single 32-bit read from address offset
00h. Reads across DWord boundaries are not supported.
Bit
Description
31:3
Buffer Descriptor List Base Address [31:3] — R/W. These bits represent address bits 31:3. The
entries should be aligned on 8-byte boundaries.
2:0 Hardwired to 0.
x_CIV—Current Index Value Register
I/O Address:
Default Value:
Lockable:
MBAR + 04h (MICIV),
MBAR + 14h (MOCIV),
00h
No
Attribute:
Size:
Power Well:
RO
8 bits
Core
Software can read the registers at offsets 04h, 05h and 06h simultaneously by performing a single,
32-bit read from address offset 04h. Software can also read this register individually by doing a
single, 8-bit read to offset 04h. Reads across DWord boundaries are not supported.
Bit
Description
7:5 Hardwired to 0.
Current Index Value [4:0] — RO. These bits represent which buffer descriptor within the list of 16
4:0 descriptors is being processed currently. As each descriptor is processed, this value is
incremented.
15.2.3
x_LVI—Last Valid Index Register
I/O Address:
Default Value:
MBAR + 05h (MILVI),
MBAR + 15h (MOLVI)
00h
Attribute:
Power Well:
R/W
Core
Software can read the registers at offsets 04h, 05h and 06h simultaneously by performing a single,
32-bit read from address offset 04h. Software can also read this register individually by doing a
single, 8-bit read to offset 05h. Reads across DWord boundaries are not supported.
Bit
Description
7:5 Hardwired to 0
4:0
Last Valid Index [4:0] — R/W. These bits indicate the last valid descriptor in the list. This value is
updated by the software as it prepares new buffers and adds to the list.
Intel^® 82801DB ICH4 Datasheet
503