82801DB Datasheet, PDF (324/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

LPC Interface Bridge Registers (D31:F0)
9.4
8259 Interrupt Controller (PIC) Registers
The interrupt controller registers are located at 20h and 21h for the master controller (IRQ0–7), and
at A0h and A1h for the slave controller (IRQ8–13). These registers have multiple functions,
depending upon the data written to them. Below is a description of the different register
possibilities for each address. Table 9-3 provides the register I/O map for the interrupt controller.
Table 9-3. Interrupt Controller I/O Address Map (PIC Registers)
Port
Aliases
Register Name/Function
20h
21h
A0h
A1h
4D0h
4D1h
24h, 28h,
2Ch, 30h,
34h, 38h, 3Ch
25h, 29h,
2Dh, 31h,
35h, 39h, 3Dh
A4h, A8h,
ACh, B0h,
B4h, B8h, BCh
A5h, A9h,
ADh, B1h,
B5h, B9h, BDh
—
—
Master PIC ICW1 Init. Cmd Word 1 Register
Master PIC OCW2 Op Ctrl Word 2 Register
Master PIC OCW3 Op Ctrl Word 3 Register
Master PIC ICW2 Init. Cmd Word 2 Register
Master PIC ICW3 Init. Cmd Word 3 Register
Master PIC ICW4 Init. Cmd Word 4 Register
Master PIC OCW1 Op Ctrl Word 1 Register
Slave PIC ICW1 Init. Cmd Word 1 Register
Slave PIC OCW2 Op Ctrl Word 2 Register
Slave PIC OCW3 Op Ctrl Word 3 Register
Slave PIC ICW2 Init. Cmd Word 2 Register
Slave PIC ICW3 Init. Cmd Word 3 Register
Slave PIC ICW4 Init. Cmd Word 4 Register
Slave PIC OCW1 Op Ctrl Word 1 Register
Master PIC Edge/Level Triggered Register
Slave PIC Edge/Level Triggered Register
Default Value
Undefined
001XXXXXb
X01XXX10b
Undefined
Undefined
01h
00h
Undefined
001XXXXXb
X01XXX10b
Undefined
Undefined
01h
00h
00h
00h
Type
WO
WO
R/W
WO
WO
WO
R/W
WO
WO
R/W
WO
WO
WO
R/W
R/W
R/W
324
Intel^® 82801DB ICH4 Datasheet