82801DB Datasheet, PDF (529/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

Electrical Characteristics
Table 17-10. IDE PIO and Multiword DMA ModeTiming
Sym
Parameter
Min Max Units Notes Figure
t60
PDIOR#/PDIOW#/SDIOR#/SDIOW# Active From
CLK66 Rising
2
20
ns
17-8,17-9
t61
PDIOR#/PDIOW#/SDIOR#/SDIOW# Inactive From
CLK66 Rising
2
20
ns
17-8,17-9
t62 PDA[2:0]/SDA[2:0] Valid Delay From CLK66 Rising
2
30
ns
17-8
t63
PDCS1#/SDCS1#, PDCS3#/SDCS3# Active From
CLK66 Rising
2
30
ns
17-8
t64
PDCS1#/SDCS1#, PDCS3#/SDCS3# Inactive From
CLK66 Rising
2
30
ns
17-8
t65 PDDACK#/SDDACK# Active From CLK66 Rising
2
20
ns
17-9
t66 PDDACK#/SDDACK# Inactive From CLK66 Rising
2
20
ns
t67 PDDREQ/SDDREQ Setup Time to CLK66 Rising
t68 PDDREQ/SDDREQ Hold From CLK66 Rising
t69
PDD[15:0]/SDD[15:0] Valid Delay From CLK66
Rising
7
ns
7
ns
2
30
ns
17-9
17-9
17-8,17-9
t70 PDD[15:0]/SDD[15:0] Setup Time to CLK66 Rising
10
ns
17-8,17-9
t71 PDD[15:0]/SDD[15:0] Hold From CLK66 Rising
7
ns
17-8,17-9
t72 PIORDY/SIORDY Setup Time to CLK66 Rising
7
ns 1
17-8
t73 PIORDY/SIORDY Hold From CLK66 Rising
7
t74 PIORDY/SIORDY Inactive Pulse Width
48
t75
PDIOR#/PDIOW#/SDIOR#/SDIOW# Pulse Width
Low
ns 1
ns
2,3
17-8
17-8
17-8,17-9
t76
PDIOR#/PDIOW#/SDIOR#/SDIOW# Pulse Width
High
3,4
17-8,17-9
NOTES:
1. IORDY is internally synchronized. This timing is to guarantee recognition on the next clock.
2. PIORDY sample point from DIOx# assertion and PDIOx# active pulse width is programmable from 2–5 PCI
clocks when the drive mode is Mode 2 or greater. Refer to the ISP field in the IDE Timing Register
3. PIORDY sample point from DIOx# assertion, PDIOx# active pulse width and PDIOx# inactive pulse width
cycle time is the compatible timing when the drive mode is Mode 0/1. Refer to the TIM0/1 field in the IDE
timing register.
4. PDIOx# inactive pulse width is programmable from 1–4 PCI clocks when the drive mode is Mode 2 or greater.
Refer to the RCT field in the IDE Timing Register.
Intel^® 82801DB ICH4 Datasheet
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