82801DB Datasheet, PDF (435/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

EHCI Controller Registers (D29:F7)
12.2.2 Host Controller Operational Registers
This section defines the enhanced host controller operational registers. These registers are located
after the capabilities registers. The operational register base must be DWord-aligned and is
calculated by adding the value in the first capabilities register (CAPLENGTH) to the base address
of the enhanced host controller register address space. All registers are 32 bits in length.
Table 12-3. Enhanced Host Controller Operational Registers
Offset
(CAPLEN
GTH+)
Mnemonic
Register Name
00–03h
04–07h
08–0Bh
0C–0Fh
10–13h
14–17h
18–1Bh
1C–3Fh
40–43h
EHCI_CMD
EHCI_STS
EHCI_INTR
FRINDEX
CTRLDSSEGMENT
PERIODICLISTBASE
ASYNCLISTADDR
CONFIGFLAG
USB EHCI Command
USB EHCI Status
USB EHCI Interrupt Enable
USB EHCI Frame Index
Control Data Structure
Segment
Period Frame List Base
Address
Next Asynchronous List
Address
Reserved
Configure Flag Register
44–47h
PORTSC0
Port 0 Status and Control
48–4Bh
PORTSC1
Port 1 Status and Control
4C–4Fh
PORTSC2
Port 2 Status and Control
50–53h
PORTSC3
Port 3 Status and Control
54–57h
PORTSC4
Port 4 Status and Control
58–5Bh
5C–5Fh
60–73h
74–3FFh
PORTSC5
Port 5 Status and Control
Reserved
Debug Port Registers
Reserved
Default
00080000h
00001000h
00000000h
00000000h
00000000h
Special
Notes
Type
R/W, RO
R/WC, RO
R/W
R/W
R/W
00000000h
R/W
00000000h
0h
00000000h
00003000h
00003000h
00003000h
00003000h
00003000h
00003000h
Undefined
Undefined
Undefined
Suspend
Suspend
Suspend
Suspend
Suspend
Suspend
Suspend
R/W
RO
R/W
R/WC,
R/W, RO
R/WC,
R/W, RO
R/WC,
R/W, RO
R/WC,
R/W, RO
R/WC,
R/W, RO
R/WC,
R/W, RO
RO
RO
RO
Note: Software must read and write these registers using only DWord accesses.These registers are
divided into two sets. The first set at offset 00:3Fh are implemented in the core power well. Unless
otherwise noted, the core-well registers are reset by the assertion of any of the following:
• core well hardware reset
• HCRESET
• D3-to-D0 reset
The second set at offset 40h to the end of the implemented register space are implemented in the
Suspend power well. Unless otherwise noted, the suspend-well registers are reset by the assertion
of either of the following:
• suspend well hardware reset
• HCRESET
Intel^® 82801DB ICH4 Datasheet
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