82801DB Datasheet, PDF (79/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

Functional Description
If any one of the above conditions does not hold, the LAN controller will use the MW command. If
a MWI cycle has started and one of the conditions is no longer valid (for example, the data space in
the memory buffer is now less than CLS), then the LAN controller terminates the MWI cycle at the
end of the cache line. The next cycle will be either a MW or MWI cycle depending on the
conditions listed above.
If the LAN controller started a MW cycle and reached a cache line boundary, it either continues or
terminates the cycle depending on the Terminate Write on Cache Line configuration bit of the LAN
controller Configure command (byte 3, bit 3). If this bit is set, the LAN controller terminates the
MW cycle and attempts to start a new cycle. The new cycle is a MWI cycle if this bit is set and all
of the above listed conditions are met. If the bit is not set, the LAN controller continues the MW
cycle across the cache line boundary if required.
Read Align
The Read Align feature enhances the LAN controller’s performance in cache line oriented systems.
In these particular systems, starting a PCI transaction on a non-cache line aligned address may
cause low performance.
In order to resolve this performance anomaly, the LAN controller attempts to terminate transmit
DMA cycles on a cache line boundary and start the next transaction on a cache line aligned
address. This feature is enabled when the Read Align Enable bit is set in the LAN controller
Configure command (byte 3, bit 2).
If this bit is set, the LAN controller operates as follows:
• When the LAN controller is almost out of resources on the transmit DMA (i.e., the transmit
FIFO is almost full), it attempts to terminate the read transaction on the nearest cache line
boundary when possible.
• When the arbitration counter’s feature is enabled (i.e., the Transmit DMA Maximum Byte
Count value is set in the Configure command), the LAN controller switches to other pending
DMAs on cache line boundary only.
Note:
1. This feature is not recommended for use in non-cache line oriented systems since it may cause
shorter bursts and lower performance.
2. This feature should be used only when the CLS register in PCI Configuration space is set to 8
or 16.
3. The LAN controller reads all control data structures (including Receive Buffer Descriptors)
from the first DWord (even if it is not required) in order to maintain cache line alignment.
Error Handling
Data Parity Errors: As an initiator, the LAN controller checks and detects data parity errors that
occur during a transaction. If the Parity Error Response bit is set (PCI Configuration Command
register, bit 6), the LAN controller also asserts PERR# and sets the Data Parity Detected bit (PCI
Configuration Status register, bit 8). In addition, if the error was detected by the LAN controller
during read cycles, it sets the Detected Parity Error bit (PCI Configuration Status register, bit 15).
Intel^® 82801DB ICH4 Datasheet
79