82801DB Datasheet, PDF (305/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

LPC Interface Bridge Registers (D31:F0)
9.1.25
9.1.26
RTC_CONF—RTC Configuration Register (LPC I/F—D31:F0)
Offset Address: D8h
Default Value: 00h
Lockable:
Yes
Attribute:
Size:
Power Well:
R/W, R/W-Special
8 bit
Core
Bit
Description
7:5 Reserved
Upper 128-byte Lock (U128LOCK) — R/W-Special.
0 = Access to these bytes in the upper CMOS RAM range have not been locked.
4 _{1 = Locks reads and writes to bytes 38h–3Fh in the upper 128-byte bank of the RTC CMOS RAM.}
Write cycles to this range will have no effect and read cycles will not return any particular
guaranteed value. This is a write once register that can only be reset by a hardware reset.
Lower 128-byte Lock (L128LOCK) — R/W-Special.
0 = Access to these bytes in the lower CMOS RAM range have not been locked.
3 _{1 = Locks reads and writes to bytes 38h–3Fh in the lower 128-byte bank of the RTC CMOS RAM.}
Write cycles to this range will have no effect and read cycles will not return any particular
guaranteed value. This is a write once register that can only be reset by a hardware reset.
Upper 128-byte Enable (U128E) — R/W.
2 0 = Disable.
1 = Enables access to the upper 128-byte bank of RTC CMOS RAM.
1:0 Reserved
COM_DEC—LPC I/F Communication Port Decode Ranges
(LPC I/F—D31:F0)
Offset Address: E0h
Default Value: 00h
Lockable:
No
Attribute:
Size:
Power Well:
R/W
8 bit
Core
Bit
Description
7 Reserved
COMB Decode Range — R/W. This field determines which range to decode for the COMB Port.
000 = 3F8h–3FFh (COM1)
001 = F8h–2FFh (COM2)
010 = 220h–227h
6:4 _{011 = 228h–22Fh}
100 = 238h–23Fh
101 = 2E8h–2EFh (COM4)
110 = 338h–33Fh
111 = 3E8h–3EFh (COM3)
3 Reserved
COMA Decode Range — R/W. This field determines which range to decode for the COMA Port.
000 = 3F8h–3FFh (COM1)
001 = 2F8h–2FFh (COM2)
010 = 220h–227h
2:0 _{011 = 228h–22Fh}
100 = 238h–23Fh
101 = 2E8h–2EFh (COM4)
110 = 338h–33Fh
111 = 3E8h–3EFh (COM3)
Intel^® 82801DB ICH4 Datasheet
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