82801DB Datasheet, PDF (143/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

Functional Description
Table 5-41. Causes of Wake Events
Cause
States Can Wake
From
How Enabled
RTC Alarm
S1–S5 ⁽¹⁾
Set RTC_EN bit in PM1_EN register
Power Button
GPI[0:n]
S1–S5
S1–S5 ⁽¹⁾
Always enabled as Wake event
GPE0_EN register
USB
S1–S5 ⁽³⁾
Set USB1_EN, USB 2_EN and USB3_EN bits in GPE0_EN
register
LAN
S1–S5
Will use PME#. Wake enable set with LAN logic.
RI#
S1–S5 ⁽¹⁾
Set RI_EN bit in GPE0_EN register
AC ’97
S1–S5
Set AC ’97_EN bit in GPE0_EN register
Primary PME#
Secondary PME#
S1–S5
S1–S5 ⁽¹⁾
PME_B0_EN bit in GPE0_EN register
Set PME_EN bit in GPE0_EN Register.
SMBALERT#
S1–S5
Always enabled as Wake event
SMBus Slave
Message
S1–S5
Wake/SMI# command always enabled as a Wake Event.
NOTE: SMBus Slave Message can wake the system from S1–
S5, as well as from S5 due to Power Button Override.
SMBus Host Notify
message received
S1–S5
HOST_NOTIFY_WKEN bit SMBus Slave Command register.
Reported in the SMB_WAK_STS bit in the GPEO_STS register.
PME_B0 (internal USB
EHCI controller)
S1–S5 ⁽¹⁾
Set PME_B0_EN bit in GPE0_EN register.
NOTES:
1. This will be a wake event from S5 only if the sleep state was entered by setting the SLP_EN and SLP_TYP
bits via software.
2. If in the S5 state due to a powerbutton override, the possible wake events are due to Power Button, Hard
Reset Without Cycling (See Command Type 3 in Table 5-95), and Hard Reset System (See Command
Type 4 in Table 5-95).
3. The entry for USB changes from being able to wake from S1–S4 to being able to wake from S1–S5. Previous
designs actively blocked wake events while in S5. There is no need to do this as software already disables
waking from USB on S5 (so the wake bits are masked), and in the future power buttons will move to USB
keyboards, and a wake from S5 will be necessary.
It is important to understand that the various GPIs have different levels of functionality when used
as wake events. The GPIs that reside in the core power well can only generate wake events from an
S1 state. Also only certain GPIs are “ACPI Compliant,” meaning that their Status and Enable bits
reside in ACPI I/O space. Table 5-42 summarizes the use of GPIs as wake events.
Table 5-42. GPI Wake Events
GPI
GPI[7:0]
GPI[13:11], GPI[8]
Power Well
Core
Resume
Wake From
S1
S1–S5
Notes
ACPI Compliant
The latency to exit the various Sleep states varies greatly and is heavily dependent on power supply
design, so much so that the exit latencies due to the ICH4 are insignificant.
Intel^® 82801DB ICH4 Datasheet
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