82801DB Datasheet, PDF (385/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

IDE Controller Registers (D31:F1)
10.1.4
10.1.5
Bit
Description
I/O Space Enable (IOSE) — R/W. This bit controls access to the I/O space registers.
0 = Disables access to the Legacy or Native IDE ports (both Primary and Secondary) as well as
the Bus Master IO registers.
1 = Enable. Note that the Base Address register for the Bus Master registers should be
programmed before this bit is set.
0
NOTES:
1. Separate bits are provided (IDE Decode Enable, in the IDE Timing register) to independently
disable the Primary or Secondary I/O spaces.
2. When this bit is 0 and the IDE controller is in Native Mode, the Interrupt Pin Register (see
Section 10.1.19) will be masked (the interrupt will not be asserted). If an interrupt occurs while
the masking is in place and the interrupt is still active when the masking ends, the interrupt will
be allowed to be asserted.
STS — Device Status Register (IDE—D31:F1)
Address Offset: 06–07h
Default Value: 0280h
Attribute: R/WC, RO
Size:
16 bits
Bit
Description
15 Detected Parity Error (DPE) — RO. Reserved as 0.
14 Signaled System Error (SSE) — RO. Reserved as 0.
Received Master Abort (RMA) — R/WC.
13 0 = Cleared by writing a 1 to it.
1 = Bus Master IDE interface function, as a master, generated a master-abort.
12 Reserved as 0 — RO.
Signaled Target Abort (STA) — R/WC.
11 ^{0 = Cleared by writing a 1 to it.}
1 = ICH4 IDE interface function is targeted with a transaction that the ICH4 terminates with a target
abort.
DEVSEL# Timing Status (DEV_STS) — RO.
10:9 _{01 = Hardwired; however, the ICH4 does not have a real DEVSEL# signal associated with the IDE}
unit, so these bits have no effect.
8 Data Parity Error Detected (DPED)— RO. Reserved as 0.
7 Fast Back to Back Capable (FB2BC)— RO. Reserved as 1.
6 User Definable Features (UDF)— RO. Reserved as 0.
5 66 MHz Capable (66MHZ_CAP)— RO. Reserved as 0.
4:0 Reserved
REVID—Revision ID Register (IDE—D31:F1)
Offset Address: 08h
Default Value: See Bit Description
Attribute:
Size:
RO
8 bits
Bit
Description
7:0
Revision Identification Value — RO. Refer to the ICH4 Specification Update for the value of the
Revision ID Register.
Intel^® 82801DB ICH4 Datasheet
385