82801DB Datasheet, PDF (142/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

Functional Description
5.12.6.2 Initiating Sleep State
Sleep states (S1–S5) are initiated by:
• Masking interrupts, turning off all bus master enable bits, setting the desired type in the
SLP_TYP field, and then setting the SLP_EN bit. The hardware will then attempt to gracefully
put the system into the corresponding Sleep state by first going to a C2 state. See
Section 5.12.5 for details on going to the C2 state.
• Pressing the PWRBTN# signal for more than 4 seconds to cause a Power Button Override
event. In this case the transition to the S5 state will be less graceful, since there will be no
dependencies on observing Stop-Grant cycles from the processor or on clocks other than the
RTC clock.
Table 5-40. Sleep Types
Sleep Type
Comment
S1
Intel^® ICH4 asserts the STPCLK# signal. It also has the option to assert the CPUSLP# signal.
This lowers the processor’s power consumption. No snooping is possible in this state.
ICH4 asserts SLP_S3#. The SLP_S3# signal will control the power to non-critical circuits.
S3
Power will only be retained to devices needed to wake from this sleeping state, as well as to
the memory.
S4
ICH4 asserts SLP_S3# and SLP_S4#. The SLP_S4# signal will shut off the power to the
memory subsystem. Only devices needed to wake from this state should be powered.
S5
Same power state as S4. ICH4 asserts SLP_S3#, SLP_S4# and SLP_S5#.
5.12.6.3
Exiting Sleep States
Sleep states (S1–S5) are exited based on Wake events. The Wake events force the system to a full
on state (S0), although some non-critical subsystems might still be shut off and have to be brought
back manually. For example, the hard disk may be shut off during a sleep state, and have to be
enabled via a GPIO pin before it can be used.
Upon exit from the ICH4-controlled Sleep states, the WAK_STS bit is set. The possible causes of
Wake Events (and their restrictions) are shown in Table 5-41.
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Intel^® 82801DB ICH4 Datasheet