82801DB Datasheet, PDF (467/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

AC ’97 Audio Controller Registers (D31:F5)
AC ’97 Audio Controller Registers
(D31:F5)
14
14.1 AC ’97 Audio PCI Configuration Space (D31:F5)
Note: Registers address locations not shown in Table 14-1 should be treated as Reserved.
Table 14-1. AC ‘97 Audio PCI Configuration Register Address Map (Audio—D31:F5)
Offset
00–01h
02–03h
04–05h
06–07h
08h
09h
0Ah
0Bh
0Eh
10–13h
14–17h
18–1Bh
1C–1Fh
2C–2Dh
2E–2Fh
34h
3Ch
3Dh
40h
41h
50–51h
52–53h
54–55h
Mnemonic
Register
VID
DID
PCICMD
PCISTS
RID
PI
SCC
BCC
HEDT
NAMBBAR
NAMBBAR
MMBAR
MBBAR
SVID
SID
CAP_PTR
INTR_LN
INTR_PN
PCID
CFG
PID
PC
PCS
Vendor Identification
Device Identification
PCI Command
PCI Device Status
Revision Identification
Programming Interface
Sub Class Code
Base Class Code
Header Type
Native Audio Mixer Base Address
Native Audio Bus Mastering Base Address
Mixer Base Address(Mem)
Bus Master Base Address(Mem)
Subsystem Vendor ID
Subsystem ID
Capabilities Pointer
Interrupt Line
Interrupt Pin
Programmable Codec ID
Configuration
PCI Power Management ID
PC -Power Management Capabilities
Power Management Control and Status
Default
8086h
24C5h
0000
0280h
See Note
00
01h
04h
00
00000001h
00000001h
00000000h
00000000h
0000h
0000h
50h
00h
02h
01h
00h
0001h
C9C2h
0000h
Access
RO
RO
R/W, RO
R/WC, RO
RO
RO
RO
RO
RO
R/W, RO
R/W, RO
R/W, RO
R/W, RO
R/WO
R/WO
RO
R/W
RO
R/W
R/W
RO
RO
R/W, R/WC
NOTE: Refer to the ICH4 Specification Update for the value of the Revision ID Register.
Note: Internal reset as a result of D3_HOT to D0 transition will reset all the core well registers except the
following BIOS programmed registers as BIOS may not be invoked following the D3-to-D0
transition. All resume well registers will not be reset by the D3_HOT to D0 transition.
Intel^® 82801DB ICH4 Datasheet
467