82801DB Datasheet, PDF (63/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

Intel^® ICH4 Power Planes and Pin States
3.5
Power Planes for Input Signals
Table 3-5 shows the power plane associated with each input signal, as well as what device drives
the signal at various times. Valid states include:
High
Low
Static: Will be high or low, but will not change
Driven: Will be high or low, and is allowed to change
Running: For input clocks
Table 3-5. Power Plane for Input Signals (Sheet 1 of 2)
Signal Name
A20GATE
AC_BIT_CLK
AC_SDIN[2:0]
APICCLK
CLK14
CLK48
CLK66
EE_DIN
FERR#
INTRUDER#
IRQ[15:14]
LAN_CLK
LAN_RXD[2:0]
LDRQ[0]#
LDRQ[1]#
OC[5:0]#
PCICLK
PDDREQ
PIORDY
PME#
PWRBTN#
PWROK
RCIN#
REQ[0:5]#
REQ[B:A]#
RI#
Power Well
Main I/O
Main I/O
Resume I/O
Main I/O
Main I/O
Main I/O
Main Logic
Resume I/O
CPU I/O
RTC
Main I/O
Resume I/O
Resume I/O
Main I/O
Main I/O
Resume I/O
Main I/O
Main I/O
Main I/O
Resume I/O
Resume I/O
RTC
Main I/O
Main I/O
Main I/O
Resume I/O
Driver During Reset
External Microcontroller
AC ’97 Codec
AC ’97 Codec
Clock Generator
Clock Generator
Clock Generator
Clock Generator
EEPROM Component
External Pull-Up
External Switch
IDE
LAN Connect Component
LAN Connect Component
LPC Devices
LPC Devices
External Pull-Ups
Clock Generator
IDE Device
IDE Device
Internal Pull-Up
Internal Pull-Up
System Power Supply
External Microcontroller
PCI Master
PC/PCI Devices
Serial Port Buffer
S1
Static
Low
Low
Running
Running
Running
Running
Driven
Static
Driven
Static
Driven
Driven
High
High
Driven
Running
Static
Static
Driven
Driven
Driven
High
Driven
Driven
Driven
S3
Low
Low
Low
Low
Low
Low
Low
Driven
High
Driven
Low
Driven
Driven
Low
Low
Driven
Low
Low
Low
Driven
Driven
Low
Low
Low
Low
Driven
S5
Low
Low
Low
Low
Low
Low
Low
Driven
High
Driven
Low
Driven
Driven
Low
Low
Driven
Low
Low
Low
Driven
Driven
Low
Low
Low
Low
Driven
Intel^® 82801DB ICH4 Datasheet
63