82801DB Datasheet, PDF (364/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

LPC Interface Bridge Registers (D31:F0)
Bit
Description
BIOS Release (BIOS_RLS) — WO.
7
0 = This bit will always return 0 on reads. Writes of 0 to this bit have no effect.
1 = Enables the generation of an SCI interrupt for ACPI software when a one is written to this bit
position by BIOS software.
Software SMI# Timer Enable (SWSMI_TMR_EN) — R/W.
0 = Disable. Clearing the SWSMI_TMR_EN bit before the timer expires will reset the timer and the
6
SMI# will not be generated.
1 = Starts Software SMI# Timer. When the SWSMI timer expires (the timeout period depends upon
the SWSMI_RATE_SEL bit setting), SWSMI_TMR_STS is set and an SMI# is generated.
SWSMI_TMR_EN stays set until cleared by software.
APMC_EN — R/W.
5 0 = Disable. Writes to the APM_CNT register will not cause an SMI#.
1 = Enables writes to the APM_CNT register to cause an SMI#.
SLP_SMI_EN — R/W.
0 = Disables the generation of SMI# on SLP_EN. Note that this bit must be 0 before the software
4
attempts to transition the system into a sleep state by writing a 1 to the SLP_EN bit.
1 = A write of 1 to the SLP_EN bit (bit 13 in PM1_CNT register) will generate an SMI#, and the
system will not transition to the sleep state based on that write to the SLP_EN bit.
LEGACY_USB_EN — R/W.
3 0 = Disable.
1 = Enables legacy USB circuit to cause SMI#.
BIOS_EN — R/W.
2 0 = Disable.
1 = Enables the generation of SMI# when ACPI software writes a 1 to the GBL_RLS bit.
End of SMI (EOS) — R/W-Special. This bit controls the arbitration of the SMI signal to the
processor. This bit must be set for the ICH4 to assert SMI# low to the processor.
0 = Once the ICH4 asserts SMI# low, the EOS bit is automatically cleared.
1 = When this bit is set, SMI# signal will be deasserted for 4 PCI clocks before its assertion. In the
1
SMI handler, the CPU should clear all pending SMIs (by servicing them and then clearing their
respective status bits), set the EOS bit, and exit SMM. This will allow the SMI arbiter to re-
assert SMI upon detection of an SMI event and the setting of a SMI status bit.
NOTE: ICH4 is able to generate 1st SMI after reset even though EOS bit is not set. Subsequent
SMI require EOS bit is set.
GBL_SMI_EN — R/W.
0 0 = No SMI# will be generated by ICH4. This bit is reset by a PCI reset event.
1 = Enables the generation of SMI# in the system upon any enabled SMI event.
364
Intel^® 82801DB ICH4 Datasheet