82801DB Datasheet, PDF (420/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

EHCI Controller Registers (D29:F7)
12.1.4
12.1.5
PCISTS—PCI Device Status Register (USB EHCI—D29:F7)
Address Offset: 06–07h
Default Value: 0290h
Attribute: R/WC, RO
Size:
16 bits
Bit
Description
15 Detected Parity Error (DPE) — RO. Reserved as 0.
Signaled System Error (SSE) — R/WC.
14 ^{0 = Software clears this bit by writing a 1 to this bit location.}
1 = ICH4 signaled SERR# (internally). The SER_EN bit (bit 8 of the Command Register) must be 1
for this bit to be set.
Received Master Abort (RMA) — R/WC.
0 = Software clears this bit by writing a 1 to this bit location.
13 _{1 = USB EHCI, as a master, received a master abort status on a memory access. This is treated as}
a Host Error and halts the DMA engines. This event can optionally generate an SERR# by
setting the SERR# Enable bit.
Received Target Abort (RTA) — R/WC.
0 = Software clears this bit by writing a 1 to this bit location.
12 _{1 = USB EHCI, as a master, received a target abort status on a memory access. This is treated as}
a Host Error and halts the DMA engines. This event can optionally generate an SERR# by
setting the SERR# Enable bit.
Signaled Target Abort (STA) — RO. Hardwired to 0. This bit is used to indicate when the USB EHCI
11 function responds to a cycle with a target abort. There is no reason for this to happen; thus, this bit is
hardwired to 0.
10:9
DEVSEL# Timing Status (DEV_STS) — RO. This 2-bit field defines the timing for DEVSEL#
assertion.
Master Data Parity Error Detected (DPED) — R/WC.
0 = Software clears this bit by writing a 1 to this bit location.
8 _{1 = ICH4 detected a data parity error on a USB EHCI read completion packet on the internal}
interface to the USB EHCI host controller (due to an equivalent data parity error on hub
interface), and bit 6 of the Command register is set to 1.
7 Fast Back to Back Capable (FB2BC) — RO. Reserved as 1.
6 User Definable Features (UDF) — RO. Reserved as 0.
5 66 MHz Capable (66MHZ_CAP) — RO. Reserved as 0.
4
Capabilities List (CAP_LIST) — RO. This bit is hardwired to 1 indicating the presence of a valid
capabilities pointer at offset 34h.
3:0 Reserved.
REVID—Revision ID Register (USB EHCI—D29:F7)
Offset Address: 08h
Default Value: See Bit Description
Attribute:
Size:
RO
8 bits
Bit
Description
7:0
Revision Identification Value — RO. Refer to the ICH4 Specification Update for the value of the
Revision ID Register.
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Intel^® 82801DB ICH4 Datasheet