82801DB Datasheet, PDF (304/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

LPC Interface Bridge Registers (D31:F0)
9.1.23
9.1.24
GEN_STA—General Status Register (LPC I/F—D31:F0)
Offset Address: D4h
Default Value: 0Xh
Lockable:
No
Attribute:
Size:
Power Well:
RO, R/W-Special
8 bit
Core
Bit
Description
7:3 Reserved
SAFE_MODE — RO.
2
0 = Intel^® ICH4 sampled AC_SDOUT low on the rising edge of PWROK.
1 = ICH4 sampled AC_SDOUT high on the rising edge of PWROK. ICH4 will force
FREQ_STRAP[3:0] bits to all 1s (safe mode multiplier).
NO_REBOOT — R/W-Special.
0 = Normal TCO Timer reboot functionality (reboot after 2nd TCO timeout). This bit cannot be set to
1
0 by software if the strap is set to No Reboot.
1 = ICH4 will disable the TCO Timer system reboot feature. This bit is set either by hardware when
SPKR is sampled high on the rising edge of PWROK, or by software writing a 1 to the bit.
0 Reserved
BACK_CNTL—Backed Up Control Register
(LPC I/F—D31:F0)
Offset Address:
Default Value:
Lockable:
D5h
0Fh
(upon RTCRST# assertion low)
2Fh
(if Safe Mode Strap is active)
No
Attribute:
Size:
Power Well:
R/W
8 bit
RTC
Bit
Description
7 Reserved. Read only as 0.
6 Reserved. Read only as 0.
Top-Block Swap Mode (TOP_SWAP) — R/W.
0 = Intel^® ICH4 will not invert A16. This bit is cleared by RTCRST# assertion, but not by any other
5
type of reset.
1 = ICH4 inverts A16 for cycles targeting FWH BIOS space (Does not affect accesses to FWH
feature space).
CPU BIST Enable (CPU_BIST_EN) — R/W.
0 = Disable.
1 = The INIT# signal will be driven active when CPURST# is active. INIT# will go inactive with the
same timings as the other CPU I/F signals (Hold Time after CPURST# inactive). Note that
4
CPURST# is generated by the memory controller hub, but the ICH4 has a hub interface special
cycle that allows the ICH4 to control the assertion/deassertion of CPURST#.
NOTE: This bit is in the Resume well and is reset by RSMRST#, but not by PCIRST# nor CF9h
writes.
CPU Frequency Strap (FREQ_STRAP[3:0]) — R/W. These bits determine the internal frequency
multiplier of the processor. These bits can be reset to 1111 based on an external pin strap or via the
3:0 RTCRST# input signal. Software must program this field based on the processor’s specified
frequency. Note that this field is only writable when the SAFE_MODE bit is cleared to 0, and
SAFE_MODE is only cleared by PWROK rising edge. These bits are in the RTC well.
304
Intel^® 82801DB ICH4 Datasheet