82801DB Datasheet, PDF (345/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

LPC Interface Bridge Registers (D31:F0)
9.8
Power Management Registers (D31:F0)
The power management registers are distributed within the PCI Device 31: Function 0 space, as
well as a separate I/O range. Each register is described below. Unless otherwise indicate, bits are in
the main (core) power well.
Bits not explicitly defined in each register are assumed to be reserved. When writing to a reserved
bit, the value should always be 0. Software should not attempt to use the value read from a reserved
bit, as it may not be consistently 1 or 0.
9.8.1 Power Management PCI Configuration Registers (D31:F0)
Table 9-8 shows a small part of the configuration space for PCI Device 31: Function 0. It includes
only those registers dedicated for power management. Some of the registers are only used for
Legacy Power management schemes.
Table 9-8. PCI Configuration Map (PM—D31:F0)
Offset
40h–43h
44h
A0h
A2h
A4h
A8h
B8–BBh
C0
C4–CAhh
CCh
Mnemonic
PM_BASE
ACPI_CNTL
GEN_PMCON_1
GEN_PMCON_2
GEN_PMCON_3
STPCLK_DEL
GPI_ROUT
TRP_FWD_EN
MON[n]_TRP_RNG
MON_TRP_MSK
Register Name
ACPI Base Address (See
Section 9.1.10)
ACPI Control (See Section 9.1.11)
General Power Management
Configuration 1
General Power Management
Configuration 2
General Power Management
Configuration 3
Stop Clock Delay Register
GPI Route Control
I/O Monitor Trap Forwarding Enable
I/O Monitor[4:7] Trap Range
I/O Monitor Trap Range Mask
Default
Type
00000001h
R/W
00h
0000h
R/W
R/W, RO,
R/WO, R/WC
0000h
R/WC, R/W
00h
0Dh
00000000h
R/W, R/WC
R/W
R/W
0000h
R/W
0000h
R/W
Intel^® 82801DB ICH4 Datasheet
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