82801DB Datasheet, PDF (459/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

SMBus Controller Registers (D31:F3)
13.2.3
13.2.4
13.2.5
Bit
Description
KILL — R/W.
0 = Normal SMBus Host controller functionality.
1 _{1 = When set, kills the current host transaction taking place, sets the FAILED status bit, and}
asserts the interrupt (or SMI#). This bit, once set, must be cleared by software to allow the
SMBus Host controller to function normally.
INTREN — R/W.
0 0 = Disable.
1 = Enable the generation of an interrupt or SMI# upon the completion of the command.
HST_CMD—Host Command Register
Register Offset: 03h
Default Value: 00h
Attribute:
Size:
R/W
8 bits
Bit
Description
7:0
This 8-bit field is transmitted by the host controller in the command field of the SMBus protocol during
the execution of any command.
XMIT_SLVA—Transmit Slave Address Register
Register Offset: 04h
Default Value: 00h
Attribute:
Size:
R/W
8 bits
This register is transmitted by the host controller in the slave address field of the SMBus protocol.
Bit
Description
7:1 ADDRESS — R/W. 7-bit address of the targeted slave.
RW — R/W. Direction of the host transfer.
0 0 = Write
1 = Read
HST_D0—Data 0 Register
Register Offset: 05h
Default Value: 00h
Attribute:
Size:
R/W
8 bits
Bit
Description
DATA0/COUNT — R/W. This field contains the eight bit data sent in the DATA0 field of the SMBus
7:0
protocol. For block write commands, this register reflects the number of bytes to transfer. This register
should be programmed to a value between 1 and 32 for block counts. A count of 0 or a count above 32
will result in unpredictable behavior. The host controller does not check or log illegal block counts.
Intel^® 82801DB ICH4 Datasheet
459