82801DB Datasheet, PDF (298/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

LPC Interface Bridge Registers (D31:F0)
9.1.14
9.1.15
9.1.16
GPIOBASE—GPIO Base Address (LPC I/F—D31:F0)
Offset Address:
Default Value:
Lockable:
58h–5Bh
00000001h
No
Attribute:
Size:
Power Well:
R/W, RO
32 bit
Core
Bit
31:16
15:6
5:1
0
Description
Reserved
Base Address — R/W. Provides the 64 bytes of I/O space for GPIO.
Reserved
Resource Indicator — RO. Hardwired to 1; indicates I/O space.
GPIO_CNTL—GPIO Control (LPC I/F—D31:F0)
Offset Address: 5Ch
Default Value: 00h
Lockable:
No
Attribute:
Size:
Power Well:
R/W
8 bit
Core
Bit
Description
7:5 Reserved
GPIO Enable (GPIO_EN) — R/W. This bit enables/disables decode of the I/O range pointed to by
the GPIO base register and enables/disables the GPIO function.
4
0 = Disable.
1 = Enable.
3:0 Reserved
PIRQ[n]_ROUT—PIRQ[A,B,C,D] Routing Control
(LPC I/F—D31:F0)
Offset Address:
Default Value:
Lockable:
PIRQA–60h, PIRQB–61h,
PIRQC–62h, PIRQD–63h
80h
No
Attribute:
Size:
Power Well:
R/W
8 bit
Core
Bit
Description
Interrupt Routing Enable (IRQEN) — R/W.
0 = The corresponding PIRQ is routed to one of the ISA-compatible interrupts specified in bits[3:0].
1 = The PIRQ is not routed to the 8259.
7
NOTE: BIOS must program this bit to 0 during POST for any of the PIRQs that are being used. The
value of this bit may subsequently be changed by the OS when setting up for I/O APIC
interrupt delivery mode.
6:4 Reserved
IRQ Routing — R/W. (ISA compatible)
0000 = Reserved 1000 = Reserved
0001 = Reserved 1001 = IRQ9
0010 = Reserved 1010 = IRQ10
3:0 _{0011 = IRQ3}
1011 = IRQ11
0100 = IRQ4
1100 = IRQ12
0101 = IRQ5
1101 = Reserved
0110 = IRQ6
1110 = IRQ14
0111 = IRQ7
1111 = IRQ15
298
Intel^® 82801DB ICH4 Datasheet