82801DB Datasheet, PDF (378/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

LPC Interface Bridge Registers (D31:F0)
9.10 General Purpose I/O Registers (D31:F0)
The control for the general purpose I/O signals is handled through a separate 64-byte I/O space.
The base offset for this space is selected by the GPIO_BAR register. Table 9-12 shows the GPIO
Register I/O address map.
Table 9-12. Registers to Control GPIO
Offset
Mnemonic
Register Name
General Registers
00–03h
04–07h
08–0Bh
0C–0Fh
10–13h
GPIO_USE_SEL GPIO Use Select
GP_IO_SEL GPIO Input/Output Select
—
Reserved
GP_LVL
GPIO Level for Input or Output
—
Reserved
Output Control Registers
14–17h
18–1Bh
1C–1Fh
GPO_TTL
GPO_BLINK
—
GPIO TTL Select
GPIO Blink Enable
Reserved
Input Control Registers
20–2Bh
2C–2Fh
30–33h
34–37h
38–3Bh
—
Reserved
GPI_INV
GPIO Signal Invert
GPIO_USE_SEL2 GPIO Use Select
GP_IO_SEL2 GPIO Input/Output Select 2
GP_LVL2
GPIO Level for Input or Output 2
Default
Access
1A003180h
R/W
0000 FFFFh
R/W
00h
RO
1F1F 0000h
R/W
00h
RO
06630000h
RO
00000000h
R/W
0
RO
00000000h
RO
00000000h
R/W
00000000h
R/W
00000000h
R/W
00000FFFh
R/W
9.10.1
GPIO_USE_SEL—GPIO Use Select Register
Offset Address:
Default Value:
Lockable:
GPIOBASE + 00h
1A003180h
Yes
Attribute:
Size:
Power Well:
R/W
32-bit
Resume
Bit
Description
21,11,
5:0
GPIO_USE_SEL — R/W. Each bit in this register enables the corresponding GPIO (if it exists) to be
used as a GPIO, rather than for the native function.
0 = Signal used as native function.
1 = Signal used as a GPIO.
NOTES:
1. Bits 31:29, 26, 15:14, and 10:9 are not implemented because there is no corresponding GPIO.
Bits 28:27, 25:22, 20:18, 13:12, and 8:6 are not implemented because the corresponding GPIOs
are not multiplexed. Bits 16:17 are not implemented because the GPIO selection is controlled by
bits 0:1. The REQ/GNT# pairs are enabled/disabled together. For example, if bit 0 is set to 1,
then the REQ/GNT[A]# pair will function as GPIO[0] and GPIO[16].
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Intel^® 82801DB ICH4 Datasheet