82801DB Datasheet, PDF (396/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

IDE Controller Registers (D31:F1)
Bit
Description
5 Primary Slave Channel Cable Reporting — R/W. Same description as bit 7
4
Primary Master Channel Cable Reporting — R/W. Same description as bit 7
Secondary Drive 1 Base Clock (SCB1) — R/W.
3 0 = 33 MHz base clock for Ultra ATA timings.
1 = 66 MHz base clock for Ultra ATA timings.
Secondary Drive 0 Base Clock (SCBO) — R/W.
2 0 = 33 MHz base clock for Ultra ATA timings.
1 = 66 MHz base clock for Ultra ATA timings.
Primary Drive 1 Base Clock (PCB1) — R/W.
1 0 = 33 MHz base clock for Ultra ATA timings.
1 = 66 MHz base clock for Ultra ATA timings.
Primary Drive 0 Base Clock (PCB0) — R/W.
0 0 = 33 MHz base clock for Ultra ATA timings.
1 = 66 MHz base clock for Ultra ATA timings.
10.2 Bus Master IDE I/O Registers (D31:F1)
The bus master IDE function uses 16 bytes of I/O space, allocated via the BMIBA register, located
in Device 31:Function 1 Configuration space, offset 20h. All bus master IDE I/O space registers
can be accessed as byte, word, or DWord quantities. Reading reserved bits returns an
indeterminate, inconsistent value, and writes to reserved bits have no affect (but should not be
attempted). The description of the I/O registers is shown below in Table 10-2.
Table 10-2. Bus Master IDE I/O Registers
Offset
00
01
02
03
04–07
08
09
0A
0B
0C–0F
Mnemonic
BMICP
BMISP
BMIDP
BMICS
BMISS
BMIDS
Register Name
Bus Master IDE Command Primary
Reserved
Default
00h
00h
Bus Master IDE Status Primary
00h
Reserved
Bus Master IDE Descriptor Table Pointer Primary
Bus Master IDE Command Secondary
Reserved
00h
xxxxxxxxh
00h
00h
Bus Master IDE Status Secondary
00h
Reserved
00h
Bus Master IDE Descriptor Table Pointer Secondary xxxxxxxxh
Type
R/W
RO
R/WC, R/W,
RO
RO
R/W
R/W
RO
R/WC, R/W,
RO
RO
R/W
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Intel^® 82801DB ICH4 Datasheet