82801DB Datasheet, PDF (577/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

Register Index
Table A-3. Intel^® ICH4 Variable I/O Registers (Sheet 5 of 6)
Register Name
Offset
Datasheet Location
Mic. 2 Last Valid Index
Mic. 2 Status Register
Mic 2 Position In Current Buffer
Mic. 2 Prefetched Index Value
Mic. 2 Control Register
PCM In 2 Buffer Descriptor list
Base Address Register
PCM In 2 Current Index Value
PCM In 2 Last Valid Index
PCM In 2 Status Register
PCM In 2 Position In Current
Buffer
PCM In 2 Prefetched Index Value
PCM In 2 Control Register
S/PDIF Buffer Descriptor list
Base Address Register
S/PDIF Current Index Value
S/PDIF Last Valid Index
S/PDIF Status Register
S/PDIF Position In Current Buffer
S/PDIF Prefetched Index Value
S/PDIF Control Register
SDATA_IN Map Register
45h
46–47h
48–49h
4Ah
4Bh
50–53h
54h
55h
56–57h
58–59h
5Ah
5Bh
60–63
64h
65h
66–67h
68–69h
6Ah
6Bh
80
Section 14.2.3, “x_LVI—Last Valid Index Register” on page 14-483
Section 14.2.4, “x_SR—Status Register” on page 14-484
Section 14.2.5, “x_PICB—Position In Current Buffer Register” on
page 14-485
Section 14.2.6, “x_PIV—Prefetched Index Value Register” on page 14-485
Section 14.2.7, “x_CR—Control Register” on page 14-486
Section 14.2.1, “x_BDBAR—Buffer Descriptor Base Address Register” on
page 14-482
Section 14.2.2, “x_CIV—Current Index Value Register” on page 14-483
Section 14.2.3, “x_LVI—Last Valid Index Register” on page 14-483
Section 14.2.4, “x_SR—Status Register” on page 14-484
Section 14.2.5, “x_PICB—Position In Current Buffer Register” on
page 14-485
Section 14.2.6, “x_PIV—Prefetched Index Value Register” on page 14-485
Section 14.2.7, “x_CR—Control Register” on page 14-486
Section 14.2.1, “x_BDBAR—Buffer Descriptor Base Address Register” on
page 14-482
Section 14.2.2, “x_CIV—Current Index Value Register” on page 14-483
Section 14.2.3, “x_LVI—Last Valid Index Register” on page 14-483
Section 14.2.4, “x_SR—Status Register” on page 14-484
Section 14.2.5, “x_PICB—Position In Current Buffer Register” on
page 14-485
Section 14.2.6, “x_PIV—Prefetched Index Value Register” on page 14-485
Section 14.2.7, “x_CR—Control Register” on page 14-486
Section 14.2.11, “SDM—SDATA_IN Map Register” on page 14-491
AC ’97 Modem I/O Registers at MBAR + Offset
MBAR is set in Section 15.1.11, “MBAR—Modem Base Address Register (Modem—D31:F6)” on page 15-497
Modem In Buffer Descriptor List
Base Address Register
Modem In Current Index Value
Register
Modem In Last Valid Index
Register
Modem In Status Register
Modem In Position In Current
Buffer Register
Modem In Prefetch Index Value
Register
Modem In Control Register
Modem Out Buffer Descriptor List
Base Address Register
Modem Out Current Index Value
Register
00h
Section 15.2.1, “x_BDBAR—Buffer Descriptor List Base Address Register”
on page 15-503
04h
Section 15.2.2, “x_CIV—Current Index Value Register” on page 15-503
05h
Section 15.2.3, “x_LVI—Last Valid Index Register” on page 15-503
06h
Section 15.2.4, “x_SR—Status Register” on page 15-504
08h
Section 15.2.5, “x_PICB—Position in Current Buffer Register” on
page 15-505
0Ah
Section 15.2.6, “x_PIV—Prefetch Index Value Register” on page 15-505
0Bh
Section 15.2.7, “x_CR—Control Register” on page 15-506
10h
Section 15.2.1, “x_BDBAR—Buffer Descriptor List Base Address Register”
on page 15-503
14h
Section 15.2.2, “x_CIV—Current Index Value Register” on page 15-503
Intel^® 82801DB ICH4 Datasheet
577