82801DB Datasheet, PDF (288/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

Hub Interface to PCI Bridge Registers (D30:F0)
8.1.27
CNF—ICH4 Configuration Register (HUB-PCI—D30:F0)
Offset Address: 50–51h
Default Value: 1400h
Attribute:
Size:
R/W
16 bits
Bit
Description
15:10
9
Reserved
High Priority PCI Enable (HP_PCI_EN) — R/W.
0 = All PCI REQ#/GNT pairs have the same arbitration priority.
1 = Enables a mode where the REQ[0]#/GNT[0]# signal pair has a higher arbitration priority.
Hole Enable (15 MB–16 MB) — R/W.
8 0 = Disable
1 = Enables the 15 MB to 16 MB hole in main memory.
7:2 Reserved
12-Clock Retry Enable — R/W. System BIOS must set this bit for PCI compliance.
0 = If this bit is not set, under the same circumstance, the bus will not be released since all other
1
masters see the lock in use.
1 = When a PCI Master is running a locked memory read or write cycle, while all other bus masters
are waiting to run locked cycles, this bit, when set allows the ICH4 to retry the cycle after 12
PCI clocks.
0 Reserved
8.1.28 MTT—Multi-Transaction Timer Register (HUB-PCI—D30:F0)
Offset Address: 70h
Default Value: 20h
Attribute:
Size:
R/W
8 bits
MTT is an 8-bit register that controls the amount of time that the ICH4’s arbiter allows a PCI
initiator to perform multiple back-to-back transactions on the PCI bus. The ICH4’s MTT
mechanism is used to guarantee a fair share of the Primary PCI bandwidth to an initiator that
performs multiple back-to-back transactions to fragmented memory ranges (and as a consequence
it can not use long burst transfers).
The number of clocks programmed in the MTT represents the guaranteed time slice (measured in
PCI clocks) allotted to the current agent, after which the arbiter will grant another agent that is
requesting the bus. The MTT value must be programmed with 8 clock granularity in the same
manner as MLT. For example, if the MTT is programmed to 18h, then the selected value
corresponds to the time period of 24 PCI clocks.The default value of MTT is 20h (32 PCI clocks).
Note:
Programming the MTT to a value of 00h disables this function, which could cause starvation
problems for some PCI master devices. Programming of the MTT to anything less than 16 clocks
will not allow the Grant-to-FRAME# latency to be 16 clocks. The MTT timer will timeout before
the Grant-to-FRAME# trigger causing a re-arbitration.
Bit
Description
Multi-Transaction Timer Count Value — R/W. This field specifies the amount of time that grant
7:3 will remain asserted to a master continuously asserting its request for multiple transfers. This field
specifies the count in an 8-clock (PCI clock) granularity.
2:0 Reserved
288
Intel^® 82801DB ICH4 Datasheet