82801DB Datasheet, PDF (232/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

Functional Description
5.19.2.1
5.19.2.2
The ICH4 has three AC_SDIN pins allowing a single, dual, or triple codec configuration. When
multiple codecs are connected, the primary, secondary, and tertiary codecs can be connected to any
AC_SDIN line. The ICH4 does not distinguish between codecs on its AC_SDIN[2:0] pins;
however, the registers do distinguish between AC_SDIN[0], AC_SDIN[1], and AC_SDIN[2] for
wake events, etc. If using a Modem Codec it is recommended to connect it to AC_SDIN[1].
See your Platform Design Guide for a matrix of valid codec configurations. The ICH4 does not
support optional test modes as outlined in the AC ’97 specification.
AC-Link Output Frame (SDOUT)
A new output frame begins with a low-to-high transition of AC_SYNC. AC_SYNC is synchronous
to the rising edge of BIT_CLK. On the immediately following falling edge of AC_BIT_CLK, the
codec samples the assertion of AC_SYNC. This falling edge marks the time when both sides of
AC-link are aware of the start of a new frame. On the next rising edge of AC_BIT_CLK, the ICH4
transitions AC_SDOUT into the first bit position of slot 0, or the valid frame bit. Each new bit
position is presented to the AC-link on a rising edge of AC_BIT_CLK, and subsequently sampled
by the codec on the following falling edge of AC_BIT_CLK. This sequence ensures that data
transitions and subsequent sample points for both incoming and outgoing data streams are time
aligned.
The output frame data phase corresponds to the multiplexed bundles of all digital output data
targeting codec DAC inputs and control registers. Each output frame supports up to twelve
outgoing data time slots. The ICH4 generates 16 or 20 bits and stuffs remaining bits with zeros.
The output data stream is sent with the most significant bit first, and all invalid slots are stuffed
with zeros. When mono audio sample streams are output from the ICH4, software must ensure both
left and right sample stream time slots are filled with the same data.
Output Slot 0: Tag Phase
Slot 0 is considered the tag phase. The tag phase is a special 16-bit time slot wherein each bit
conveys a valid tag for its corresponding time slot within the current frame. A one in a given bit
position of slot 0 indicates that the corresponding time slot within the current frame has been
assigned to a data stream and contains valid data. If a slot is tagged invalid with a zero in the
corresponding bit position of slot 0, the ICH4 stuffs the corresponding slot with zeros during that
slot’s active time.
Within slot 0, the first bit is a valid frame bit (slot 0, bit 15) which flags the validity of the entire
frame. If the valid frame bit is set to one, this indicates that the current frame contains at least one
slot with valid data. When there is no transaction in progress, the ICH4 will deassert the frame
valid bit. Note that after a write to slot 12, that slot will always stay valid, and therefore the frame
valid bit will remain set.
The next 12 bit positions of slot 0 (bits [14:3]) indicate which of the corresponding twelve time
slots contain valid data. Bits [1:0] of slot 0 are used as codec ID bits to distinguish between
separate codecs on the link.
Using the valid bits in the tag phase allows data streams of differing sample rates to be transmitted
across the link at its fixed 48 kHz frame rate. The codec can control the output sample rate of the
ICH4 using the SLOTREQ bits as described in the AC ’97 specification.
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Intel^® 82801DB ICH4 Datasheet