82801DB Datasheet, PDF (87/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

Functional Description
5.3.1.1 LPC Cycle Types
The ICH4 implements all of the cycle types described in the Low Pin Count Interface
Specification, Revision 1.0. Table 5-2 shows the cycle types supported by the ICH4.
Table 5-2. LPC Cycle Types Supported
Cycle Type
Memory Read
Memory Write
I/O Read
I/O Write
DMA Read
DMA Write
Bus Master Read
Bus Master Write
Comment
Single: 1 byte only
Single: 1 byte only
1 byte only. Intel^® ICH4 breaks up 16- and 32-bit processor cycles into multiple 8-bit
transfers. (See Note 1)
1 byte only. ICH4 breaks up 16- and 32-bit processor cycles into multiple 8-bit
transfers. (See Note 1)
Can be 1, or 2 bytes
Can be 1, or 2 bytes
Can be 1, 2, or 4 bytes. (See Note 2)
Can be 1, 2, or 4 bytes. (See Note 2)
NOTES:
1. For memory cycles below 16 MB which do not target enabled FWH ranges, the ICH4 performs standard LPC
memory cycles. It only attempts 8-bit transfers. If the cycle appears on PCI as a 16-bit transfer, it will appear
as two consecutive 8-bit transfers on LPC. Likewise, if the cycle appears as a 32-bit transfer on PCI, it will
appear as four consecutive 8-bit transfers on LPC. If the cycle is not claimed by any peripheral, it will be
subsequently aborted, and the ICH4 will return a value of all ones to the processor. This is done to maintain
compatibility with ISA memory cycles where pull-up resistors would keep the bus high if no device responds.
2. Bus Master Read or Write cycles must be naturally aligned. For example, a 1-byte transfer can be to any
address. However, the 2-byte transfer must be word aligned (i.e., with an address where A0=0). A DWord
transfer must be DWord aligned (i.e., with an address where A1and A0 are both 0).
5.3.1.2 Start Field Definition
Table 5-3. Start Field Bit Definitions
Bits[3:0]
Encoding
0000
0010
0011
1111
Start of cycle for a generic target
Grant for bus master 0
Grant for bus master 1
Stop/Abort: End of a cycle for a target.
Definition
NOTE: All other encodings are RESERVED.
Intel^® 82801DB ICH4 Datasheet
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