82801DB Datasheet, PDF (406/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

USB UHCI Controllers Registers
Bit
Description
SMI at End of Pass-through Enable (SMIATENDPS) — R/W. May need to cause SMI at the end of
a pass-through. Can occur if an SMI is generated in the middle of a pass through, and needs to be
7 ^{serviced later.}
0 = Disable
1 = Enable
Pass Through State (PSTATE) — RO.
6 0 = If software needs to reset this bit, it should set bit 5 in all of the host controllers to 0.
1 = Indicates that the state machine is in the middle of an A20GATE pass-through sequence.
A20Gate Pass-Through Enable (A20PASSEN) — R/W.
5 ^{0 = Disable.}
1 = Allows A20GATE sequence Pass-Through function. A specific cycle sequence involving writes to
port 60h and 64h does not result in the setting of the SMI status bits.
SMI on USB IRQ Enable (USBSMIEN) — R/W.
4 0 = Disable
1 = USB interrupt will cause an SMI event.
SMI on Port 64 Writes Enable (64WEN) — R/W.
3 0 = Disable
1 = A 1 in bit 11 will cause an SMI event.
SMI on Port 64 Reads Enable (64REN) — R/W.
2 0 = Disable
1 = A 1 in bit 10 will cause an SMI event.
SMI on Port 60 Writes Enable (60WEN) — R/W.
1 0 = Disable
1 = A 1 in bit 9 will cause an SMI event.
SMI on Port 60 Reads Enable (60REN) — R/W.
0 0 = Disable
1 = A 1 in bit 8 will cause an SMI event.
11.1.17
USB_RES—USB Resume Enable Register
(USB—D29:F0/F1/F2)
Address Offset:
C4h
Default Value:
00h
Attribute:
Size:
R/W
8 bits
Bit
Description
7:2 Reserved
PORT1EN — R/W. Enable port 1 of the USB controller to respond to wakeup events.
1 0 = The USB controller will not look at this port for a wakeup event.
1 = The USB controller will monitor this port for remote wakeup and connect/disconnect events.
PORT0EN — R/W. Enable port 0 of the USB controller to respond to wakeup events.
0 0 = The USB controller will not look at this port for a wakeup event.
1 = The USB controller will monitor this port for remote wakeup and connect/disconnect events.
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Intel^® 82801DB ICH4 Datasheet