82801DB Datasheet, PDF (205/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

Functional Description
5.17.10 USB 2.0 EHCI Based Debug Port
The ICH4 supports the elimination of the legacy COM ports by providing the ability for new
debugger software to interact with devices on a USB EHCI port. High-level restrictions and
features are:
• Must be operational before USB EHCI drivers are loaded.
• Must work even when the port is disabled.
• Must work even though non-configured port is default-routed to the classic controller. Note
that the Debug Port can not be used to debug an issue that requires a classic USB device on
Port #0 using the UHCI drivers.
• Must allow normal system USB EHCI traffic in a system that may only have one USB port.
• Debug Port device (DPD) must be High-Speed capable and connect to a High-Speed port on
ICH4 systems.
• Debug Port FIFO must always make forward progress (a bad status on USB is simply
presented back to software)
• The Debug Port FIFO is only given one USB access per microframe
The Debug port facilitates OS and device driver debug. It allows the software to communicate with
an external console using a USB EHCI connection. Because the interface to this link does not go
through the normal USB EHCI stack, it allows communication with the external console during
cases where the OS is not loaded, the USB EHCI software is broken, or where the USB EHCI
software is being debugged. Specific features of this implementation of a debug port are:
• Only works with an external USB 2.0 debug device (console)
• Implemented for a specific port on the host controller
• Operational anytime the port is not suspended AND the host controller is in D0 power state.
• Capability is interrupted when port is driving USB RESET
5.17.10.1 Theory of Operation
There are two operational modes for the USB debug port:
• Mode 1 is when the USB port is in a disabled state from the viewpoint of a standard host
controller driver. In Mode 1, the Debug Port controller is required to generate a “keepalive”
packets less than 2 ms apart to keep the attached debug device from suspending. The keepalive
packet should be a standalone 32-bit SYNC field.
• Mode 2 is when the host controller is running (i.e., Host controller’s Run/Stop# bit is 1). In
Mode 2, the normal transmission of SOF packets will keep the debug device from suspending.
Behavioral Rules
1. In both modes 1 and 2, the Debug Port controller must check for software requested debug
transactions at least every 125 microseconds.
2. If the debug port is enabled by the debug driver, and the standard host controller driver resets
the USB port, USB debug transactions are held off for the duration of the reset and until after
the first SOF is sent.
3. If the standard host controller driver suspends the USB port, then USB debug transactions are
held off for the duration of the suspend/resume sequence and until after the first SOF is sent.
4. The ENABLED_CNT bit in the debug register space is independent of the similar port control
bit in the associated Port Status and Control register.
Intel^® 82801DB ICH4 Datasheet
205