82801DB Datasheet, PDF (48/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

Signal Description
Table 2-11. Processor Interface Signals (Sheet 2 of 2)
Name
RCIN#
A20GATE
CPUPWRGD
Type
I
I
OD
Description
Keyboard Controller Reset CPU: The keyboard controller can generate INIT#
to the processor. This saves the external OR gate with the ICH4’s other
sources of INIT#. When the ICH4 detects the assertion of this signal, INIT# is
generated for 16 PCI clocks.
NOTE: The ICH4 ignores RCIN# assertion during transitions to the S3, S4
and S5 states.
A20 Gate: A20GATE is from the keyboard controller. The signal acts as an
alternative method to force the A20M# signal active. It saves the external OR
gate needed with various other PCIsets.
CPU Power Good: This signal should be connected to the processor’s
PWRGOOD input. This is an open-drain output signal (external pull-up resistor
required) that represents a logical AND of the ICH4’s PWROK and
VRMPWRGD signals.
2.12 SMBus Interface
Table 2-12. SM Bus Interface Signals
Name
SMBDATA
SMBCLK
SMBALERT#/
GPIO[11]
Type
I/OD
I/OD
I
Description
SMBus Data: External pull-up is required.
SMBus Clock: External pull-up is required.
SMBus Alert: This signal is used to wake the system or generate SMI#. If not
used for SMBALERT#, it can be used as a GPI.
2.13 System Management Interface
Table 2-13. System Management Interface Signals
Name
INTRUDER#
SMLINK[1:0]
Type
I
I/OD
Description
Intruder Detect: This signal can be set to disable the system if the box is
detected open. This signal’s status is readable, so it can be used like a GPI if
the Intruder Detection is not needed.
System Management Link: SMBus link to optional external system
management ASIC or LAN controller. External pull-ups are required. Note that
SMLINK[0] corresponds to an SMBus Clock signal and SMLINK[1]
corresponds to an SMBus Data signal.
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Intel^® 82801DB ICH4 Datasheet