82801DB Datasheet, PDF (123/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

Functional Description
5.8.5.4 Registers Associated with Processor System Bus Interrupt Delivery
Capabilities Indication
The capability to support Processor System Bus interrupt delivery is indicated via ACPI
configuration techniques. This involves the BIOS creating a data structure that gets reported to the
ACPI configuration software.
DT Bit in the Boot Configuration Register
This enables the ICH4 to deliver interrupts as memory writes. This bit is ignored if the APIC mode
is not enabled.
5.8.5.5 Interrupt Message Format
The ICH4 writes the message to PCI (and to the Host controller) as a 32-bit memory write cycle. It
uses the formats shown in Table 5-25 and Table 5-26 for the Address and Data.
The local APIC (in the processor) has a delivery mode option to interpret Processor System Bus
messages as a SMI in which case the processor treats the incoming interrupt as a SMI instead of as
an interrupt. This does not mean that the ICH4 has any way to have a SMI source from ICH4 power
management logic cause the I/OAPIC to send an SMI message (there is no way to do this). The
ICH4’s I/OAPIC can only send interrupts due to interrupts which do not include SMI, NMI or
INIT. This means that in IA32/IA64 based platforms, Processor System Bus interrupt message
format delivery modes 010 (SMI/PMI), 100 (NMI), and 101 (INIT) as indicated in this section,
must not be used and is not supported. Only the hardware pin connection is supported by ICH4.
:
Table 5-25. Interrupt Message Address Format
Bit
31:20
19:12
11:4
3
2
1:0
Description
Will always be FEEh
Destination ID: This will be the same as bits 63:56 of the I/O Redirection Table entry for the
interrupt associated with this message.
Extended Destination ID: This will be the same as bits 55:48 of the I/O Redirection Table entry for
the interrupt associated with this message.
Redirection Hint: This bit is used by the processor host bridge to allow the interrupt message to be
redirected.
0 = The message will be delivered to the agent (processor) listed in bits 19:12.
1 = The message will be delivered to an agent with a lower interrupt priority This can be derived
from bits 10:8 in the Data Field (see below).
The Redirection Hint bit will be a 1 if bits 10:8 in the delivery mode field associated with
corresponding interrupt are encoded as 001 (Lowest Priority). Otherwise, the Redirection Hint bit
will be 0.
Destination Mode: This bit is used only when the Redirection Hint bit is set to 1. If the Redirection
Hint bit and the Destination Mode bit are both set to 1, then the logical destination mode is used,
and the redirection is limited only to those processors that are part of the logical group as based on
the logical ID.
Will always be 00.
Intel^® 82801DB ICH4 Datasheet
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