82801DB Datasheet, PDF (568/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

Register Index
Table A-1. Intel^® ICH4 PCI Configuration Registers (Sheet 8 of 10)
Register Name
Debug Port Capability ID
Next Item Ptr #2
Debug Port Base Offset
USB Release Number
Frame Length Adjustment
Power Wake Capabilities
USB EHCI Legacy Support Extended
Capability
USB EHCI Legacy Support Control/
Status
Intel Specific USB EHCI SMI
Access Control
USB HS Reference Voltage Register
Vendor ID
Device ID
Command Register
Device Status
Revision ID Register
Sub Class Code
Base Class Code
SMB Base Address Register
Subsystem Vendor ID Register
Subsystem ID Register
Interrupt Line
Interrupt Pin
Offset
Datasheet Location
58h
59h
5A–5Bh
60h
61h
62–63h
68–6Bh
6C–6Fh
70–73h
80h
DC–DFh
Section 12.1.20, “DEBUG_CAPID—Debug Port Capability ID Register
(USB EHCI—D29:F7)” on page 12-425
Section 12.1.21, “NXT_PTR2—Next Item Pointer #2 Register (USB
EHCI—D29:F7)” on page 12-426
Section 12.1.22, “DEBUG_BASE—Debug Port Base Offset Register (USB
EHCI—D29:F7)” on page 12-426
Section 12.1.23, “USB_RELNUM—USB Release Number Register (USB
EHCI—D29:F7)” on page 12-426
Section 12.1.24, “FL_ADJ—Frame Length Adjustment Register (USB
EHCI—D29:F7)” on page 12-427
Section 12.1.25, “PWAKE_CAP—Port Wake Capability Register (USB
EHCI—D29:F7)” on page 12-427
Section 12.1.26, “LEG_EXT_CAP—USB EHCI Legacy Support Extended
Capability Register (USB EHCI—D29:F7)” on page 12-428
Section 12.1.27, “LEG_EXT_CS—USB EHCI Legacy Support Extended
Control / Status Register (USB EHCI—D29:F7)” on page 12-428
Section 12.1.28, “SPECIAL_SMI—Intel Specific USB EHCI SMI Register
(USB EHCI—D29:F7)” on page 12-430
Section 12.1.29, “ACCESS_CNTL—Access Control Register (USB
EHCI—D29:F7)” on page 12-431
Section 12.1.30, “HS_Ref_V—USB HS Reference Voltage Register (USB
EHCI—D29:F7)” on page 12-431
SMBus Controller (D31:F3)
00–01h
02–03h
04–05h
06–07h
08h
0Ah
0Bh
20–23h
2C–2Dh
2E–2Fh
3Ch
3Dh
Section 13.1.1, “VID—Vendor Identification Register (SMBUS—D31:F3)”
on page 13-451
Section 13.1.2, “DID—Device Identification Register (SMBUS—D31:F3)”
on page 13-451
Section 13.1.3, “CMD—Command Register (SMBUS—D31:F3)” on
page 13-452
Section 13.1.4, “STA—Device Status Register (SMBUS—D31:F3)” on
page 13-452
Section 13.1.5, “REVID—Revision ID Register (SMBUS—D31:F3)” on
page 13-453
Section 13.1.6, “SCC—Sub Class Code Register (SMBUS—D31:F3)” on
page 13-453
Section 13.1.7, “BCC—Base Class Code Register (SMBUS—D31:F3)” on
page 13-453
Section 13.1.8, “SMB_BASE—SMBUS Base Address Register (SMBUS—
D31:F3)” on page 13-453
Section 13.1.9, “SVID — Subsystem Vendor ID (SMBUS—D31:F2/F4)” on
page 13-454
Section 13.1.10, “SID — Subsystem ID (SMBUS—D31:F2/F4)” on
page 13-454
Section 13.1.11, “INTR_LN—Interrupt Line Register (SMBUS—D31:F3)”
on page 13-454
Section 13.1.12, “INTR_PN—Interrupt Pin Register (SMBUS—D31:F3)”
on page 13-454
568
Intel^® 82801DB ICH4 Datasheet