82801DB Datasheet, PDF (329/587 Pages) Intel Corporation – Intel 82801DB I/O Controller Hub 4 (ICH4)

LPC Interface Bridge Registers (D31:F0)
9.4.9
Bit
Description
4:3 OCW3 Select — WO. When selecting OCW3, bits 4:3 = 01
Poll Mode Command — WO.
0 = Disable. Poll Command is not issued.
2 _{1 = Enable. The next I/O read to the interrupt controller is treated as an interrupt acknowledge cycle.}
An encoded byte is driven onto the data bus, representing the highest priority level requesting
service.
Register Read Command — WO. These bits provide control for reading the In-Service Register
(ISR) and the Interrupt Request Register (IRR). When bit 1=0, bit 0 will not affect the register read
selection. When bit 1=1, bit 0 selects the register status returned following an OCW3 read. If bit 0=0,
the IRR will be read. If bit 0=1, the ISR will be read. Following ICW initialization, the default OCW3
port address read will be “read IRR”. To retain the current selection (read ISR or read IRR), always
write a 0 to bit 1 when programming this register. The selected register can be read repeatedly
1:0 ^{without reprogramming OCW3. To select a new status register, OCW3 must be reprogrammed prior}
to attempting the read.
00 = No Action
01 = No Action
10 = Read IRQ Register
11 = Read IS Register
ELCR1—Master Controller Edge/Level Triggered Register
Offset Address: 4D0h
Default Value: 00h
Attribute:
Size:
R/W
8 bits
In edge mode, (bit[x] = 0), the interrupt is recognized by a low to high transition. In level mode
(bit[x] = 1), the interrupt is recognized by a high level. The cascade channel, IRQ2, the heart beat
timer (IRQ0), and the keyboard controller (IRQ1), cannot be put into level mode.
Bit
IRQ7 ECL — R/W.
7 _{0 = Edge.}
1 = Level.
IRQ6 ECL — R/W.
6 _{0 = Edge.}
1 = Level.
IRQ5 ECL — R/W.
5 _{0 = Edge.}
1 = Level.
IRQ4 ECL — R/W.
4 0 = Edge.
1 = Level.
IRQ3 ECL — R/W.
3 _{0 = Edge.}
1 = Level.
2:0 Reserved. Must be 0.
Description
Intel^® 82801DB ICH4 Datasheet
329